• Compliant to industrywide, 10 G link specifications
• Uses a highly reliable, 850 nm oxide VCSEL
• Lead-free and RoHS 6/6-compliant, with allowed exemptions
• Commercial case operating temperature 0
–
70°C;
extended temperature operating up to 85°
• Single 3.3 V power supply
• Low power consumption (typically 450 mW)
• Bit error rate < 1 x 10
-12
• Hot pluggable
Applications
• High-speed local area networks
- Switches and routers
- Network interface cards
• Computer cluster crossconnect systems
• Custom high-bandwidth data pipes
Compliance
•
•
•
•
•
•
•
•
•
•
SFF 8431 Revision 3.2
SFF 8432 Revision 5.0
SFF 8472 Revision 10.3
IEEE 802.3 Clause 52 10GBASE-SR
and 10GBASE-SW
10 G Fibre Channel
CDRH and IEC60825-1 Class 1 Laser
Eye Safety
FCC Class B
ESD Class 2 per MIL-STD 883
Method 3015
UL 94, V0
Reliability tested per Telcordia GR-468
The lead-free and RoHS-compliant small form factor pluggable (SFP+) transceiver
from JDSU improves the performance for 10 Gigabit Ethernet (10 G) applications,
and is ideal for high-speed, local area network applications. This transceiver
features a highly reliable, 850 nm, oxide, vertical-cavity surface-emitting laser
(VCSEL) coupled to an LC optical connector. The transceiver is fully compliant to
10GBASE-SR, 10GBASE-SW and 10 G Fibre Channel specifications, with internal
AC coupling on both transmit and receive data signals. The all-metal housing
design provides low EMI emissions in demanding 10 G applications and conforms
to IPF specifications. An enhanced digital diagnostic feature set allows for real-
time monitoring of transceiver performance and system stability, and the serial ID
allows for customer and vendor system information to be stored in the transceiver.
Transmit disable, loss-of-signal, and transmitter fault functions are also provided.
The small size of the transceiver allows for high-density board designs that, in
turn, enable greater total bandwidth.
NORTH AMERICA: 800 498-JDSU (5378)
WORLDWIDE: +800 5378-JDSU
WEBSITE: www.jdsu.com
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPLIANT
2
Section 1
Functional Description
The PLRXPL-Sx-S43-22-N 10 G SFP+ 850 nm optical transceiver is designed to
transmit and receive 64B/66B scrambled 10 G serial optical data over 50/125 µm
or 62.5/125 µm multimode optical fiber.
Transmitter
The transmitter converts 64B/66B scrambled serial PECL or CML electrical data
into serial optical data compliant with the 10GBASE-SR, 10GBASE-SW or 10 G
Fibre channel standard. Transmit data lines (TD+ and TD-) are internally AC
coupled, with 100
Ω
differential termination.
Transmitter rate select (RS1) pin 9 is assigned to control the SFP+ module trans-
mitter rate. It is connected internally to a 30 kΩ pull-down resistor. A data signal
on this pin does not affect the operation of the transmitter.
An open collector-compatible transmit disable (Tx_Disable) is provided. This pin
is internally terminated with a 10 kΩ resistor to V
cc,T
. A logic “1,” or no connec-
tion, on this pin will disable the laser from transmitting. A logic “0” on this pin
provides normal operation.
The transmitter has an internal PIN monitor diode that ensures constant optical
power output, independent of supply voltage. It is also used to control the laser
output power over temperature to ensure reliability at high temperatures.
An open collector-compatible transmit fault (Tx_Fault) is provided. The Tx_
Fault signal must be pulled high on the host board for proper operation. A logic
“1” output from this pin indicates that a transmitter fault has occurred or that
the part is not fully seated and the transmitter is disabled. A logic “0” on this pin
indicates normal operation.
Receiver
The receiver converts 64B/66B scrambled serial optical data into serial PECL/CML
electrical data. Receive data lines (RD+ and RD-) are internally AC coupled with
100
Ω
differential source impedance, and must be terminated with a 100
Ω
dif-
ferential load.
Receiver Rate Select (RS0) pin 7 is assigned to control the SFP+ module receiver
rate. It is connected internally to a 30 kΩ pull-down resistor. A data signal on this
pin has no affect on the operation of the receiver.
An open collector compatible loss of signal (LOS) is provided. The LOS must be
pulled high on the host board for proper operation. A logic “0” indicates that light
has been detected at the input to the receiver (see Optical characteristics, Loss of
Signal Assert/Deassert Time). A logic “1” output indicates that insufficient light
has been detected for proper operation.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPLIANT
3
16 Transmitter
Power Supply
10 kΩ
3 Transmitter
Disable In
VCC_TX TX_DIS
TD+
18 Transmitter
Positive Data
TOSA
Laser Driver
TX_GND
TX_FAULT
TD -
100
Ω
19 Transmitter
Negative Data
2 Transmitter
Fault Out
1, 17, 20 Transmitter
Signal Ground
SCL
Management Processor
SDA
EEPROM
5 SCL
Serial ID Clock
4 SDA
Serial ID Data
6 MOD_ABS
15 Receiver
Power Supply
VCC_RX
VCC_RX
RD -
50
Ω
12 Receiver
Negative Data Out
13 Receiver
Positive Data Out
8 Loss of Signal Out
9 RS1 TX Rate Select
Not Functional on
-N modules
7 RS0 RX Rate Select
Not Functional on
-N modules
10, 11, 14 Receiver
Signal Ground
ROSA
RX_GND
Receiver
RD +
RX_GND
LOS
50
Ω
30 kΩ
30 kΩ
Figure 1
SFP+ optical transceiver functional block diagram
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPLIANT
4
Section 2
Vcc
Z
*
= 100
Ω
1 VeeT
VeeT 20
R2
*
50
Ω
Vcc
2 Tx Fault
TD- 19
R1
*
50
Ω
Application Schematic
10 kΩ
Receiver (Tx Fault)
CMOS, TTL, or
Open Collector Driver
(Tx Disable)
PECL Driver
(TX DATA)
Rp***
Open Collector
Bidirectional
SDA
Vcc
3 Tx Disable
TD+ 18
Power Supply Filter
4 SDA
VeeT 17
C3
C6
Rx
L1
Vcc +3.3V
Input
Rq
Open Collector
Bidirectional
SCL
***
Vcc
Vcc
5 SCL
VccT 16
L2
C2
C1
6 MOD_ABS
VccR 15
C4
C5
Ry
10 kΩ
Mod_ABS
CMOS or TTL Driver
(RS0 Rx Rate Select)
Vcc
9 RS1
10 kΩ
Receiver (LOS)
R6
∗∗
CMOS or TTL Driver
(RS1 Tx Rate Select)
Vcc
10 VeeR
R5
∗∗
7 RS0
VeeR 14
8 LOS
RD+ 13
Z
*
= 100
Ω
RD-
12
R3
*
50
Ω
VeeR 11
R4
*
50
Ω
PECL Receiver
(RX DATA)
Figure 2
Recommended application schematic for the 10 G SFP+ optical transceiver
Notes
Power supply filtering components should be placed as close to the V
cc
pins of the host connector as possible for optimal performance.
PECL driver and receiver components will require biasing networks. Please consult application notes from suppliers of these components. CML I/O on the PHY are sup-
ported. Good impedance matching for the driver and receiver is required.
SDA and SCL should be bi-directional open collector connections in order to implement serial ID in JDSU SFP+ transceiver modules.
R1/R2 and R3/R4 are normally included in the output and input of the PHY. Please check the application notes for the IC in use.
* Transmission lines should be 100
Ω
differential traces. Vias and other transmission line discontinuities should be avoided. In order to meet the host TP1 output jitter and
TP4 jitter tolerance requirements it is recommended that the PHY has both transmitter pre-emphasis to equalize the transmitter traces and receiver equalization to equalize the
receiver traces. With appropriate transmitter pre-emphasis and receiver equalization, up to 8 dB of loss at 5 GHz can be tolerated.
** R5 and R6 are required when an Open Collector driver is used in place of CMOS or TTL drivers. 5 kΩ value is appropriate.
*** The value of R
p
and R
q
depend on the capacitive loading of these lines and the two wire interface clock frequency. See SFF-8431. A value of 10 kΩ is appropriate for 80 pF
capacitive loading at 100 kHz clock frequency.
10 G SFP+ 850 NM LIMITING TRANSCEIVER,
10 GIGABIT ETHERNET COMPLIANT
5
Power supply filtering is recommended for both the transmitter and receiver. Fil-
tering should be placed on the host assembly as close to the Vcc pins as possible for
optimal performance. V
cc,R
and V
cc,T
should have separate filters.
Power supply filter component values from Figure 2 are shown in the table below
for two different implementations.
Power Supply Filter Component Values
Component
L1, L2
Rx, Ry
C1, C5
C2, C3, C4
C6
Option A
1.0
0.5*
10
0.1
Not required
Option B
4.7
0.5*
22
0.1
22
Units
µH
Ω
µF
µF
µF
Notes:
Option A is recommended for use in applications with space constraints. Power supply noise must be less than 100 mV
p-p
.
Option B is used in the module compliance board in SFF-8431.
*If the total series resistance of L1+C6 and L2+C5 exceeds the values of Rx and Ry in the table, then Rx and Ry can be omitted.
FPGA/CPLD
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