HD66325A (TFT Driver)
64-level Grayscale Driver for the TFT
Liquid Crystal Display for XGA Systems
ADE-207-296(Z)
Rev.0.1
April 1999
Description
The HD66325A is a TFT driver LSI suitable for XGA systems (eight HD66325As used). It receives 6-
bit-per-pixel digital display data, and generates and outputs voltages for 64 grayscales. The output
circuit includes an operational amplifier and is capable of alternating outputs of positive-polarity and
negative-polarity voltages on individual output pins. This results in a high-quality display with
minimal crosstalk.
The effective output voltage deviation is limited to about
±
2 mV by incorporating the original
chopper-type amplifier circuit.
Features
•
High-speed operation
Operating clock: 40 MHz
•
Operational power-supply voltage range
V
CC
= 3.0 to 3.6 V
V
LCD
= 5 to 7 V
•
LCD drive voltage
Low-voltage side: GND to V
LCD
/2 (V)
High-voltage side: V
LCD
/2 to V
LCD
(V)
•
384 LCD drive circuits
•
Output voltage deviation
±2
mV (effective value)
HD66325A
•
Multicolor display
The HD66325A receives 6-bit-per-pixel digital display data, and selects and outputs a display
voltage from 64 grayscale voltages, enabling a maximum of 260,000 display colors when using
R/G/B color filters.
•
36 data bits (6 grayscale code bits
×
3 RGB dots
×
2 pixels)
•
Dot inversion drive
The voltage can be alternated between positive polarity and negative polarity on individual
output pins, allowing a dot-by-dot inversion drive even with a single-sided layout configuration.
This provides a high-quality display with minimal crosstalk. Also, since both positive-polarity
and negative-polarity voltages are generated by an externally provided reference power supply,
either an asymmetric or a symmetric drive can be used according to the characteristics of the
liquid crystal.
•
N-raster-row inversion drive
The polarity can be inverted by each N-raster-rows. The charge or discharge current under the
TFT load can be lowered and flicker on the specific display can be reduced.
•
Chopper-type operational amplifier
The output circuit includes an operational amplifier, which enables the external reference power
supply circuit to be configured using only resistance ladders. In addition, use of the chopper-
type amplifier eliminates output voltage deviations between frames and ensures high-quality
displays.
•
Bidirectional shift
•
Chip-enable signal generation circuit
•
Package
TCP (customized package dimensions)
•
Supported systems
XGA (1024
×
768 dot) notebook PCs, monitors, and other OA equipment
2
HD66325A
Pin Arrangement
Y384
Y383
Y382
Y381
Y380
Y379
Y378
Y377
Y376
Top View
The TCP package dimensions are
not standardized.
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
EIO2
D55
D54
D53
D52
D51
D50
D45
D44
D43
11
12
13
14
15
16
17
18
19
20
D42
D41
D40
D35
D34
D33
D32
D31
D30
LC
21
22
23
24
25
26
27
28
29
30
VCC
TESTOUT
SHL
V9
V8
V7
V6
V5
VLCD
GND2
31
32
33
34
35
36
37
38
39
40
V4
V3
V2
V1
V0
GND1
CL2
CL1
M
POL2
41
42
43
44
45
46
47
48
49
50
POL1
D25
D24
D23
D22
D21
D20
D15
D14
D13
51
52
53
54
55
56
57
58
59
60
D12
D11
D10
D05
D04
D03
D02
D01
D00
EIO1
Figure 1 Pin Arrangement
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
61 FRM
3
HD66325A
Internal Block Diagram
CL2
EIO1
Clock control
EIO2
M
SHL
CL1
D55 to D50, D45 to D40,
Data
D35 to D30, D25 to D20,
inversion
D15 to D10, D05 to D00
circuit
POL1
POL2
V
LCD
V
CC
GND
Grayscale voltage
generation
64 positive-polarity
grayscales
Latch address selector
6 planes
384 latch circuits (1)
6 planes
384 latch circuits (2)
V0 to V4
384 decoders
64 negative-polarity
grayscales
V5 to V9
FRM
LC
384 output amplifier circuits
Y1Y2Y3Y4
Y384
Figure 2 Block Diagram
1. Clock control unit
Generates the chip-enable signals (EIO1, EIO2) and controls internal timing signals.
2. Data inversion circuit
Uses the POL1 and POL2 signals to perform polarity inversion (at high levels) or non-inversion (at
low levels) processing of input display data.
3. Latch address selector
Generates latch signals for sequentially latching the input display data.
4. Latch circuits (1)
384
×
6-bit latch circuits that sequentially latch 6-output
×
6-bit input display data.
5. Latch circuits (2)
Performs latching, in synchronization with CL1, of the 384
×
6-bit data latched by latch circuits (1).
4
HD66325A
6. Decoders
Decodes the 6-bit data and selects the liquid-crystal application voltages.
7. Grayscale voltage generation unit
Performs resistance-division of the external input voltage, and generates 64 positive-polarity
grayscales and 64 negative-polarity grayscales.
8. Output amplifier circuits
Outputs the grayscale voltage that has been selected for each output and buffered in the operational
amplifier.
5
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