74AHC273-Q100;
74AHCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
Rev. 1 — 27 March 2013
Product data sheet
1. General description
The 74AHC273-Q100; 74AHCT273-Q100 is a high-speed Si-gate CMOS device and is
pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard No. 7-A.
The 74AHC273-Q100; 74AHCT273-Q100 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops
simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Qn) of the flip-flop.
All outputs are forced LOW, independent of clock or data inputs, by a LOW on the MR
input.
The device is useful for applications where only the true output is required and the clock
and master reset are common to all storage elements.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Ideal buffer for MOS microcontroller or memory
Common clock and master reset
Input levels:
For 74AHC273-Q100: CMOS level
For 74AHCT273-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74AHC273-Q100; 74AHCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AHC273-Q100
74AHC273D-Q100
74AHC273PW-Q100
74AHC273BQ-Q100
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO20
TSSOP20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
Description
Version
Type number
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
SOT764-1
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
20 terminals; body 2.5
4.5
0.85 mm
SO20
TSSOP20
plastic small outline package; 20 leads;
body width 7.5 mm
74AHCT273-Q100
74AHCT273D-Q100
40 C
to +125
C
SOT163-1
74AHCT273PW-Q100
40 C
to +125
C
74AHCT273BQ-Q100
40 C
to +125
C
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
SOT764-1
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
20 terminals; body 2.5
4.5
0.85 mm
4. Functional diagram
CP
MR
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
MR
1
mna763
11
1
C1
R
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1D
2
5
6
9
12
15
16
19
mna764
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74AHC_AHCT273_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 27 March 2013
2 of 19
NXP Semiconductors
74AHC273-Q100; 74AHCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
D0
D1
D2
D3
D
Q
D
Q
D
Q
D
Q
CP
FF1
R
D
CP
CP
FF2
R
D
CP
FF3
R
D
CP
FF4
R
D
MR
Q0
D4
D5
Q1
D6
Q2
D7
Q3
D
Q
D
Q
D
Q
D
Q
CP
FF5
R
D
CP
FF6
R
D
CP
FF7
R
D
CP
FF8
R
D
Q4
Q5
Q6
Q7
001aae056
Fig 3.
Logic diagram
3
4
7
8
13
14
17
18
1
11
D0
D1
D2
D3
D4
D5
D6
D7
MR
CP
FF1
TO
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
001aae055
Fig 4.
Functional diagram
74AHC_AHCT273_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 27 March 2013
3 of 19
NXP Semiconductors
74AHC273-Q100; 74AHCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
$+&4
$+&74
WHUPLQDO
LQGH[ DUHD
9
&&
4
'
'
4
4
'
*1'
'
4
*1'
&3
05
4
'
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
aaa-006756
74AHC273-Q100
74AHCT273-Q100
'
4
4
'
'
4
GND 10
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO20 and TSSOP20
Fig 6.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
MR
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
D0, D1, D2, D3, D4, D5, D6, D7
GND
CP
V
CC
Pin description
Pin
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
Description
master reset input (active LOW)
flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH edge-triggered)
supply voltage
74AHC_AHCT273_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 27 March 2013
4 of 19
NXP Semiconductors
74AHC273-Q100; 74AHCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
6. Functional description
Table 3.
Function table
[1]
Control
MR
Reset (clear)
Load ‘1’
Load ‘0’
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
= LOW-to-HIGH;
X = don’t care.
Operating mode
Input
CP
X
Dn
X
h
l
Output
Qn
L
H
L
L
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
0.5
0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
C
mW
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
20
20
25
-
75
65
T
amb
=
40 C
to +125
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO20 packages: above 70
C
the value of P
tot
derates linearly at 8 mW/K.
For TSSOP20 packages: above 60
C
the value of P
tot
derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60
C
the value of P
tot
derates linearly at 4.5 mW/K.
74AHC_AHCT273_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 27 March 2013
5 of 19
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