74AHC273; 74AHCT273
Rev. 4 — 23 September 2020
Octal D-type flip-flop with reset; positive-edge trigger
Product data sheet
1. General description
The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with
Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs
and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all
flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced
LOW, independent of clock or data inputs, by a LOW on the MR input.
The device is useful for applications where only the true output is required and the clock and
master reset are common to all storage elements.
2. Features
•
•
•
•
•
•
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Ideal buffer for MOS microcontroller or memory
Common clock and master reset
Input levels:
•
For 74AHC273: CMOS level
•
For 74AHCT273: TTL level
ESD protection:
•
HBM JESD22-A114E exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
•
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
•
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC273D
74AHCT273D
74AHC273PW
74AHCT273PW
74AHC273BQ
74AHCT273BQ
-40 °C to +125 °C
-40 °C to +125 °C
TSSOP20
-40 °C to +125 °C
SO20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT360-1
SOT764-1
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
Nexperia
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
4. Functional diagram
CP
MR
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
MR
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
11
1
C1
R
2
5
6
9
12
15
16
19
mna764
D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
1D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna763
Fig. 1.
Logic symbol
D0
D1
Fig. 2.
D2
IEC logic symbol
D3
D
Q
D
Q
D
Q
D
Q
CP
FF1
R
D
CP
CP
FF2
R
D
CP
FF3
R
D
CP
FF4
R
D
MR
Q0
D4
D5
Q1
D6
Q2
D7
Q3
D
Q
D
Q
D
Q
D
Q
CP
FF5
R
D
CP
FF6
R
D
CP
FF7
R
D
CP
FF8
R
D
Q4
Q5
Q6
Q7
001aae056
Fig. 3.
Logic diagram
74AHC_AHCT273
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 4 — 23 September 2020
2 / 16
Nexperia
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
D0
D1
D2
D3
D4
D5
D6
D7
MR
CP
001aae055
3
4
7
8
13
14
17
18
1
11
FF1
TO
FF8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
Fig. 4.
Functional diagram
5. Pinning information
5.1. Pinning
74AHC273
74AHCT273
terminal 1
index area
Q0
D0
2
3
4
5
6
7
8
9
GND 10
CP 11
GND
(1)
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
MR
1
74AHC273
74AHCT273
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
001aai066
D1
Q1
Q2
D2
D3
Q3
001aai067
Transparent top view
GND 10
Fig. 5.
Pin configuration SOT163-1 (SO20) and
SOT360-1 (TSSOP20)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 6.
Pin configuration SOT764-1 (DHVQFN20)
5.2. Pin description
Table 2. Pin description
Symbol
MR
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
D0, D1, D2, D3, D4, D5, D6, D7
GND
CP
V
CC
Pin
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
Description
master reset input (active LOW)
flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH edge-triggered)
supply voltage
74AHC_AHCT273
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 4 — 23 September 2020
3 / 16
Nexperia
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
↑ = LOW-to-HIGH; X = don’t care.
Operating mode
Reset (clear)
Load ‘1’
Load ‘0’
Control
MR
L
H
H
CP
X
↑
↑
Input
Dn
X
h
l
Output
Qn
L
H
L
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
-0.5
-0.5
Max
+7.0
+7.0
-
+20
+25
+75
-
+150
500
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
< -0.5 V
V
O
< -0.5 V or V
O
> V
CC
+ 0.5 V
V
O
= -0.5 V to (V
CC
+ 0.5 V)
[1]
[1]
-20
-20
-25
-
-75
-65
T
amb
= -40 °C to +125 °C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT163-1 (SO20) package: P
tot
derates linearly with 12.3 mW/K above 109 °C.
For SOT360-1 (TSSOP20) package: P
tot
derates linearly with 10.0 mW/K above 100 °C.
For SOT764-1 (DHVQFN20) package: P
tot
derates linearly with 12.9 mW/K above 111 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and V
CC
= 3.3 V ± 0.3 V
fall rate
V
CC
= 5.0 V ± 0.5 V
Conditions
Min
2.0
0
0
-40
-
-
74AHC273
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
Min
4.5
0
0
-40
-
-
74AHCT273
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
°C
ns/V
ns/V
Unit
74AHC_AHCT273
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 4 — 23 September 2020
4 / 16
Nexperia
74AHC273; 74AHCT273
Octal D-type flip-flop with reset; positive-edge trigger
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74AHC273
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
V
I
= V
IH
or V
IL
HIGH-level
output voltage
I
O
= -50 μA; V
CC
= 2.0 V
I
O
= -50 μA; V
CC
= 3.0 V
I
O
= -50 μA; V
CC
= 4.5 V
I
O
= -4.0 mA; V
CC
= 3.0 V
I
O
= -8.0 mA; V
CC
= 4.5 V
V
OL
V
I
= V
IH
or V
IL
LOW-level
output voltage
I
O
= 50 μA; V
CC
= 2.0 V
I
O
= 50 μA; V
CC
= 3.0 V
I
O
= 50 μA; V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
C
O
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.58
3.94
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.0
3.0
4.5
-
-
0
0
0
-
-
-
-
3
4
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.36
0.36
0.1
4.0
10
-
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.48
3.80
-
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.44
0.44
1.0
40
10
-
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.40
3.70
-
-
-
-
-
-
-
-
-
-
-
-
0.5
0.9
1.65
-
-
-
-
-
0.1
0.1
0.1
0.55
0.55
2.0
80
10
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
μA
μA
pF
pF
Conditions
Min
25 °C
Typ
Max
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Max
Min
Max
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
output
capacitance
74AHC_AHCT273
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 4 — 23 September 2020
5 / 16
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