74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 3 — 12 October 2020
Product data sheet
1. General description
The 74ABT74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP),
set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored
in the flip-flop and appear at the Q output. This device is fully specified for partial power down
applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
2. Features and benefits
•
•
•
•
•
•
•
Supply voltage range from 4.5 V to 5.5 V
BiCMOS high speed and output drive
Direct interface with TTL levels
Power-up 3-state
I
OFF
circuitry provides partial Power-down mode operation
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74ABT74D
74ABT74PW
-40 °C to +85 °C
-40 °C to +85 °C
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Nexperia
74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
4. Functional diagram
4 10
1SD 2SD
2
12
3
11
1D
D
2D
1CP
CP
2CP
SD
1Q
Q
2Q
1Q
2Q
5
9
6
8
4
3
2
1
S
C1
1D
R
5
6
FF
Q
10
11
12
13
mna418
S
C1
1D
R
mna419
9
8
RD
1RD 2RD
1 13
Fig. 1.
Logic symbol
nSD
Fig. 2.
IEC logic symbol
nRD
Q
nCP
Q
nD
aaa-024200
Fig. 3.
Logic diagram for one flip-flop
5. Pinning information
5.1. Pinning
74ABT74
1RD
1D
1CP
1SD
1Q
1Q
GND
1
2
3
4
5
6
7
aaa-024201
14 V
CC
13 2RD
12 2D
11 2CP
10 2SD
9
8
2Q
2Q
74ABT74
1RD
1D
1CP
1SD
1Q
1Q
GND
1
2
3
4
5
6
7
aaa-024202
14 V
CC
13 2RD
12 2D
11 2CP
10 2SD
9
8
2Q
2Q
Fig. 4.
Pin configuration SOT108-1 (SO14)
Fig. 5.
Pin configuration SOT402-1 (TSSOP14)
74ABT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 12 October 2020
2 / 13
Nexperia
74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
5.2. Pin description
Table 2. Pin description
Symbol
1RD, 2RD
1D, 2D
1CP, 2CP
1SD, 2SD
1Q, 2Q
1Q, 2Q
GND
V
CC
Pin
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
output
complement output
ground (0 V)
supply voltage
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one setup time prior to low-to-high clock transition
L = LOW voltage level; l = LOW voltage level one setup time prior to low-to-high clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
Input
nSD
L
H
L
H
H
[1]
Output
nRD
H
L
L
H
H
nCP
X
X
X
↑
↑
nD
X
X
X
h
l
nQ
H
L
H
H
L
nQ
L
H
H
L
H
Operating mode
Asynchronous set
Asynchronous reset
Undetermined
[1]
Load "1"
Load "0"
This setup is unstable and changes when either set or reset returns to the high level.
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
Conditions
[1]
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
Min
-0.5
-1.2
-0.5
-18
-50
-
-
-65
Max
+7.0
+7.0
+5.5
-
-
40
150
+150
Unit
V
V
V
mA
mA
mA
°C
°C
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74ABT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 12 October 2020
3 / 13
Nexperia
74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
8. Recommended operating conditions
Table 5. Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
Δt/ΔV
T
amb
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
-15
-
0
-40
Typ
-
-
-
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
20
10
+85
Unit
V
V
V
V
mA
mA
ns/V
°C
9. Static characteristics
Table 6. Static characteristics
Symbol Parameter
V
IK
V
OH
V
OL
I
I
I
OFF
I
CEX
I
O
I
CC
ΔI
CC
input clamping voltage
HIGH-level output
voltage
LOW-level output
voltage
input leakage current
power-off leakage
current
output high leakage
current
output current
supply current
additional supply
current
input capacitance
Conditions
Min
V
CC
= 4.5 V; I
IK
= -18 mA
V
CC
= 4.5 V; I
OH
= -15 mA;
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OL
= 20 mA;
V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 0 V; V
I
or V
O
≤ 4.5 V
HIGH-state; V
O
= 5.5 V; V
CC
= 5.5 V;
V
I
= GND or V
CC
V
CC
= 5.5 V; V
O
= 2.5 V
V
CC
= 5.5 V; V
I
= GND or V
CC
per input pin; V
CC
= 5.5 V;
one input at 3.4 V;
other inputs at V
CC
or GND
V
I
= 0 V or V
CC
[2]
[1]
-1.2
2.5
-
-
-
-
-50
-
-
25 °C
Typ
-0.9
2.9
0.35
±0.01
±5.0
5.0
-75
2
0.25
Max
-
-
0.5
±1.0
±100
50
-180
50
500
-40 °C to +85 °C Unit
Min
-1.2
2.5
-
-
-
-
-50
-
-
Max
-
-
0.5
±1.0
±100
50
-180
50
500
V
V
V
μA
μA
μA
mA
μA
μA
C
I
[1]
[2]
-
3
-
-
-
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input at 3.4 V.
74ABT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 12 October 2020
4 / 13
Nexperia
74ABT74
Dual D-type flip-flop with set and reset; positive edge-trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; for test circuit, see
Fig. 9.
Symbol Parameter
Conditions
25 °C; V
CC
= 5.0 V
Min
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
sk(o)
t
su
t
h
t
W
t
rec
[1]
-40 °C to +85 °C; Unit
V
CC
= 5.0 V ± 0.5 V
Min
150
1.0
1.0
1.0
1.0
-
2.6
2.4
0
2.1
2.2
2.4
Max
-
4.7
4.0
6.2
5.2
0.6
-
-
-
-
-
-
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Typ
250
3.0
2.5
3.4
2.9
0.5
1.4
1.4
-1.4
1.0
1.3
1.4
Max
-
4.2
3.5
4.9
4.5
0.6
-
-
-
-
-
-
maximum frequency nCP; see
Fig. 6
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
output skew time
set-up time
hold time
pulse width
recovery time
nD to nCP HIGH; see
Fig. 6
nD to nCP LOW; see
Fig. 6
nD to nCP HIGH or LOW; see
Fig. 6
nCP HIGH or LOW; see
Fig. 6
nSD, nRD LOW; see
Fig. 7
nSD, nRD to nCP; see
Fig. 8
nCP to nQ, nQ; see
Fig. 6
nCP to nQ, nQ; see
Fig. 6
nSD, nRD to nQ, nQ; see
Fig. 7
nSD, nRD to nQ, nQ; see
Fig. 7
[1]
180
1.0
1.0
1.0
1.0
-
2.6
2.4
0
1.7
2.0
2.1
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
74ABT74
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 3 — 12 October 2020
5 / 13
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