Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
FEATURES
•
8-bit positive edge triggered register
•
3-State output buffers
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT374A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.
•
Power-up 3-State
•
Power-up reset
•
Live insertion/extraction permitted
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled; V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
3.4
3.8
4
7
110
UNIT
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIP
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT374A N
74ABT374A D
74ABT374A DB
74ABT374A PW
NORTH AMERICA
74ABT374A N
74ABT374A D
74ABT374A DB
74ABT374APW DH
DWG NUMBER
SOT146-1
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
OE
D0-D7
FUNCTION
Output enable input (active-Low)
Data inputs
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
1
3, 4, 7, 8,
13, 14, 17,
18
2, 5, 6, 9,
12, 15, 16,
19
11
10
20
Q0-Q7
CP
GND
V
CC
Data outputs
Clock pulse input (active rising edge)
Ground (0V)
Positive supply voltage
GND 10
SA00110
1995 Sep 06
1
853-1448 15704
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
LOGIC SYMBOL
3
4
7
8
13 14 17
18
LOGIC SYMBOL (IEEE/IEC)
1
11
EN
C1
D0 D1 D2 D3 D4 D5 D6 D7
11
1
CP
OE
3
4
7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
8
13
2
5
6
9
12 15 16
19
14
17
1D
2
5
6
9
12
15
16
19
SA00111
18
SA00112
FUNCTION TABLE
INPUTS
OE
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↑
=
↑
=
CP
↑
↑
↑
↑
Dn
l
h
X
X
INTERNAL
REGISTER
L
H
NC
NC
OUTPUTS
Q0 – Q7
L
H
NC
Z
Hold
OPERATING MODE
Latch and read register
Disable outputs
↑
Dn
Dn
Z
High voltage level
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
No change
Don’t care
High impedance “off” state
Low-to-High clock transition
not a Low-to-High clock transition
LOGIC DIAGRAM
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
11
CP
1
OE
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
SA00113
1995 Sep 06
2
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
PARAMETER
MIN
4.5
0
2.0
0.8
–32
64
10
+85
MAX
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
1995 Sep 06
3
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
MIN
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
OH
High-level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
OL
V
RST
I
I
I
OFF
I
PU
/I
PD
I
OZH
I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
Low-level output voltage
Power-up output low voltage
3
Input leakage current
Power-off leakage current
Power-up/down 3-State
output current
3-State output High current
3-State output Low current
Output High leakage current
Output current
1
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 0.0V; I
O
= 1mA; V
I
= GND or V
CC
;
V
OE
= Don’t Care
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3–State;
V
I
= GND or V
CC
V
CC
= 5.5V; one input at 3.4V,
other inputs at V
CC
or GND
–50
2.5
3.0
2.0
TYP
–0.9
2.9
3.4
2.4
0.42
0.13
±0.01
±5.0
±5.0
5.0
–5.0
5.0
–100
110
24
110
0.5
0.55
0.55
±1.0
±100
±50
50
–50
50
–180
250
30
250
1.5
–50
MAX
–1.2
2.5
3.0
2.0
0.55
0.55
±1.0
±100
±50
50
–50
50
–180
250
30
250
1.5
T
amb
= –40°C
to +85°C
MIN
MAX
–1.2
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
mA
UNIT
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Min
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock frequency
Propagation delay
CP to Qn
Output enable time
to High and Low level
Output disable time
from High and Low level
1
1
3
4
3
4
200
1.7
2.0
1.2
2.2
1.8
1.5
T
amb
= +25
o
C
V
CC
= +5.0V
Typ
300
3.4
3.8
3.5
4.3
3.6
3.0
4.5
4.9
4.5
5.4
4.7
4.1
Max
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
±0.5V
Min
200
1.7
2.0
1.2
2.2
1.8
1.5
5.1
5.2
5.4
6.2
5.2
4.3
Max
ns
ns
ns
ns
UNIT
1995 Sep 06
4
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
CP pulse width
High or Low
2
2
1
1.5
1.2
1.0
1.0
2.0
2.8
Typ
0.6
0.3
–0.3
–0.5
0.8
1.0
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
±0.5V
Min
1.5
1.2
1.0
1.0
2.0
2.8
ns
ns
ns
UNIT
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
1/f
MAX
OE
V
M
t
PZH
t
w
(H)
t
PHL
Qn
VM
t
w
(L)
t
PLH
VM
Qn
V
M
V
OH
–0.3V
0V
V
M
t
PHZ
CP
VM
VM
VM
SA00056
SA00066
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Dn
CP
NOTE:
The shaded areas indicate when the input is permitted
to change for predictable output performance.
1995 Sep 06
ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ
É
ÉÉÉÉÉÉÉÉÉÉ ÉÉÉ
É
V
M
V
M
V
M
V
M
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
V
M
V
M
OE
V
M
t
PZL
V
M
t
PLZ
Qn
V
M
V
OL
+0.3V
0V
SA00107
SA00067
Waveform 2. Data Setup and Hold Times
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
5
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