INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7403
4-Bit x 64-word FIFO register;
3-state
Product specification
Supersedes data of October 1990
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
FEATURES
•
Synchronous or asynchronous
operation
•
3-state outputs
•
30 MHz (typical) shift-in and
shift-out rates
•
Readily expandable in word and bit
dimensions
•
Pinning arranged for easy board
layout: input pins directly opposite
output pins
•
Output capability: driver (8 mA)
•
I
CC
category: LSI.
APPLICATIONS
•
High-speed disc or tape controller
•
Communications buffer.
GENERAL DESCRIPTION
The 74HC/HCT7403 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no.7A.
The “7403” is an expandable, First-In
First-Out (FIFO) memory organized
as 64 words by 4 bits. A guaranteed
15 MHz data-rate makes it ideal for
high-speed applications. A higher
data-rate can be obtained in
applications where the status flags
are not used (burst-mode).
With separate controls for shift-in (SI)
and shift-out (SO), reading and
writing operations are completely
independent, allowing synchronous
and asynchronous data transfers.
Additional controls include a
master-reset input (MR), an output
enable input (OE) and flags. The
data-in-ready (DIR) and
data-out-ready (DOR) flags indicate
the status of the device.
Note
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
74HC/HCT7403
TYP.
SYMBOL
t
PHL
/t
PLH
f
max
C
I
C
PD
PARAMETER
propagation delay SO,
SI to DIR and DOR
maximum clock
frequency
input capacitance
power dissipation
capacitance per
package
note 1
CONDITIONS
HC
C
L
= 15 pF;
V
CC
= 5 V
15
30
3.5
475
HCT
17
30
3.5
490
ns
MHz
pF
pF
UNIT
1. For HC the condition is V
I
= GND to V
CC
.
For HCT the condition is V
I
= GND to V
CC
−1.5
V.
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
74HC/HCT7403N
74HC/HCT7403D
PACKAGE
PINS
16
16
PIN POSITION
DIL
SO16L
MATERIAL
plastic
plastic
CODE
SOT38Z
SOT162
September 1993
2
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
PINNING
SYMBOL
OE
DIR
SI
D
O
to D
3
GND
MR
Q
3
to Q
0
DOR
SO
V
CC
1
2
3
4, 5,
6, 7
8
9
PIN
DESCRIPTION
output enable input (active LOW)
data-in-ready output
shift-in input (active HIGH)
parallel data input
DIR
2
3
4
handbook, halfpage
74HC/HCT7403
OE
1
16 V
CC
15 SO
14 DOR
13 Q0
ground
asynchronous master-reset
input (active LOW)
SI
D0
D1
D2
D3
GND
7403
5
6
7
8
MGA672
10, 11, data output
12, 13
14
15
16
data-out-ready output
shift-out input (active LOW)
positive supply voltage
12 Q1
11 Q2
10 Q3
9
MR
Fig.1 Pin configuration.
handbook, halfpage
handbook, halfpage
1
1
FIFO 64 x 4
EN4
1Z2
[IR] 3
[OR] 6
2
14
OE
4
5
6
7
D0
D1
D2
D3
SI
SO
MR
9
MGA674
Q0
Q1
Q2
Q3
DOR
DIR
13
12
11
10
3
9
15
CTR
1 ( /C2) CT
<
64
CT = 0
CT
>
0
5
5Z6
G1
G5
3
15
14
2
4
5
6
7
2D
4
13
12
11
10
MGA676
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
DOR A
SO A
SI
DIR
DATA INPUT
4
SI A
DIR A
DnA
MR
MR
OE
OE
SI B
DIR B
DOR B
SOB
DOR
SO
4
DATA OUTPUT
7403
FIFO A
Q nA
4
DnB
7403
Q nB
FIFO B
MR
OE
MGA679
Fig.4 Functional diagram.
FUNCTIONAL DESCRIPTION
A DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D
0
to D
3
is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
A DOR flag indicates the output stage
status, either data available (DOR =
HIGH) or busy (DOR = LOW). When
SO and DOR are HIGH, data is
available at the outputs (Q
0
to Q
3
).
When SO is set LOW new data may
be shifted into the output stage, once
complete DOR is set HIGH.
Expanded format
(see Fig.17)
The DOR and DIR signals are used to
allow the “7403” to be cascaded. Both
parallel and serial expansion is
possible.
Serial expansion is only possible with
typical devices.
Parallel expansion
Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
Serial expansion
Serial expansion is accomplished by:
•
tying the data outputs of the first
device to the data inputs of the
second device
•
connecting the DOR pin of the first
device to the SI pin of the second
device
•
connecting the SO pin of the first
device to the DIR pin of the second
device.
September 1993
4
ull pagewidth
R (1)
R
DOR
S
Q
FP
September 1993
SO
Philips Semiconductors
MR
61 x
SI
(1)
R
R FF1
S
Q
S
Q
S
Q
S
R FF2
R
FF3
to
FF63
R FF64
Q
Q
R
Q
R
Q
R
Q
(2)
(2)
(2)
(1)
R
FS
R
S
FB
Q
4-Bit x 64-word FIFO register; 3-state
S
Q
5
OE
CL
CL
CL
CL
CL
CL
CL
Q0
Q1
4
LATCHES
4
LATCHES
4
LATCHES
3-STATE
OUTPUT
BUFFER
Q2
Q3
position 2
position 3 to 63
position 64
MSB118
DIR
D0
CL
D1
4
LATCHES
D2
D3
position 1
(see control flip-flops)
LOW on S input of flip-flops FS, FB and FP will set Q output to HIGH independent of state on R input.
LOW on R input of FF1 to FF64 will set Q output to LOW independent of state on S input.
74HC/HCT7403
Product specification
Fig.5 Logic diagram.
FPGA/CPLD
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