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74LVC157A-Q100
Quad 2-input multiplexer
Rev. 2 — 2 May 2013
Product data sheet
1. General description
The 74LVC157A-Q100 is a quad 2-input multiplexer which select four bits of data from two
sources under the control of a common select input (S). The four outputs present the
selected data in the true (non-inverted) form. The enable input (E) is active LOW. When
pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other
input conditions. Moving the data from two groups of registers to four common output
buses is a common use of the 74LVC157A-Q100. The state of the common data select
input (S) determines the particular register from which the data comes. It can also be used
as function generator.
It is useful for implementing highly irregular logic by generating any 4 of the 16 different
functions of two variables with one variable common.
The device is the logic implementation of a 4-pole, 2-position switch, where the position of
the switch is determined by the logic levels applied to pin S.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
NXP Semiconductors
74LVC157A-Q100
Quad 2-input multiplexer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC157AD-Q100
74LVC157ADB-Q100
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT109-1
SOT338-1
Type number
74LVC157APW-Q100
40 C
to +125
C
74LVC157ABQ-Q100
40 C
to +125
C
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
SOT763-1
DHVQFN16 plastic dual In-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5
3.5
0.85 mm
4. Functional diagram
1
15
G1
EN
2
2
3
5
6
11
10
14
13
3
5
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1
1
15
S
E
1Y
4
2Y
7
3Y
9
4Y
12
mna481
1
1
MUX
4
6
11
10
14
13
mna482
7
9
12
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
2
3
5
6
11
10
14
13
1I0
1I1
2I0
2Y
2I1
3I0
3I1
4I0
4I1
4Y 12
SELECTOR
MULTIPLEXER
OUTPUTS
7
1Y
4
3Y
9
S
1
E
15
mna483
Fig 3.
74LVC157A_Q100
Functional diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 2 May 2013
2 of 17
NXP Semiconductors
74LVC157A-Q100
Quad 2-input multiplexer
S
E
1I1
1Y
1I0
2I1
2Y
2I0
3I1
3Y
3I0
4I1
4Y
4I0
mna484
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
/9&$4
6
,
,
<
,
,
<
*1'
DDD
/9&$4
9
&&
(
,
,
<
,
,
<
WHUPLQDO
LQGH[ DUHD
,
,
<
,
,
<
9
&&
(
,
,
<
,
,
<
DDD
*1'
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
74LVC157A_Q100
Pin configuration for SO16 and (T)SSOP16
Fig 6.
Pin configuration for DHVQFN16
© NXP B.V. 2013. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 2 — 2 May 2013
*1'
6
3 of 17
NXP Semiconductors
74LVC157A-Q100
Quad 2-input multiplexer
5.2 Pin description
Table 2.
Symbol
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
3Y
3I1
3I0
4Y
4I1
4I0
E
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
common data select input
data input from source 0
data input from source 1
multiplexer output
data input from source 0
data input from source 1
multiplexer output
ground (0 V)
multiplexer output
data input from source 1
data input from source 0
multiplexer output
data input from source 1
data input from source 0
enable input (active LOW)
supply voltage
6. Functional description
Table 3.
Input
E
H
L
L
L
L
[1]
Function table
[1]
Output
S
X
L
L
H
H
nI0
X
L
H
X
X
nI1
X
X
X
L
H
nY
L
L
H
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care
74LVC157A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 2 May 2013
4 of 17
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