Si 5 7 0 / S i 5 7 1
P
R E L I M I N A R Y
D
A TA
S
H E E T
A
N Y
- R
A T E
I
2
C P
R O G R A M M A B L E
XO/VCXO
Features
Any-rate programmable output
frequencies from 10 to 945 MHz and
select frequencies to 1.4 GHz
I
2
C serial interface
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available LVPECL, CMOS,
LVDS, and CML outputs
Industry-standard 5x7 mm
package
Pb-free/RoHS-compliant
1.8, 2.5, or 3.3 V supply
Si5602
Applications
SONET / SDH
xDSL
10 GbE LAN / WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Ordering Information:
See page 21.
Description
The Si570 XO/Si571 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are
user-programmable to any output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz with <1 ppb resolution. The device is programmed
via an I
2
C serial interface. Unlike traditional XO/VCXOs where a different
crystal is required for each output frequency, the Si57x uses one fixed-
frequency crystal and a DSPLL clock synthesis IC to provide any-rate
frequency operation. This IC-based approach allows the crystal resonator to
provide exceptional frequency stability and reliability. In addition, DSPLL
clock synthesis provides superior supply noise rejection, simplifying the task
of generating low-jitter clocks in noisy environments typically found in
communication systems.
Pin Assignments:
See page 20.
(Top View)
SDA
7
NC
1
2
3
8
SCL
6
5
4
V
DD
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK-
CLK+
Si570
SDA
7
Fixed
Frequency
XO
Any-rate
10-1400 MHz
®
DSPLL Clock
Synthesis
V
C
SCL
1
2
3
8
SCL
6
5
4
V
DD
SDA
OE
GND
CLK–
CLK+
Si571 only
ADC
OE
V
C
GND
Si571
Si570/Si571
Rev. 0.31 8/07
Copyright © 2007 by Silicon Laboratories
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si570/Si571
T
A B L E O F
C
O N T E N TS
Section
Page
1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. Frequency Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2. Frequency Programming Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Si570 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. Si571 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8. Si57x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Rev. 0.31
3
Si570/Si571
1. Detailed Block Diagrams
V
DD
GND
f
XTAL
+
RFREQ
M
DCO
f
osc
÷HS_DIV
÷N1
CLKOUT+
CLKOUT–
Frequency
Control
OE
SDA
SCL
Control
Interface
NVM
RAM
Figure 1. Si570 Detailed Block Diagram
V
DD
GND
f
XTAL
V
C
ADC
VCADC
+
RFREQ
M
DCO
f
osc
÷HS_DIV
÷N1
CLKOUT+
CLKOUT–
Frequency
Control
OE
SDA
SCL
Control
Interface
NVM
RAM
Figure 2. Si571 Detailed Block Diagram
4
Rev. 0.31
Si570/Si571
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
1
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Output enabled
LVPECL
CML
LVDS
CMOS
TriState mode
Output Enable (OE)
2
Min
2.97
2.25
1.71
—
—
—
—
—
0.75 x V
DD
—
–40
Typ
3.3
2.5
1.8
120
108
99
90
60
—
—
—
Max
3.63
2.75
1.89
130
117
108
98
75
—
0.5
85
Units
V
Supply Current
I
DD
mA
V
IH
V
IL
T
A
V
ºC
Operating Temperature Range
Notes:
1.
Selectable parameter specified by part number. See Section "7. Ordering Information" on page 21 for further details.
2.
OE pin includes a 17 kΩ pullup resistor to V
DD
or a 17 kΩ pulldown to GND depending on the OE polarity specified in
the part number. See "7. Ordering Information" on page 21.
Table 2. V
C
Control Voltage Input
Parameter
Symbol
Test Condition
Min
Typ
33
45
90
135
180
356
±1
±5
10.0
—
V
DD
/2
Max
Units
Control Voltage Tuning Slope
1,2,3
K
V
V
C
10 to 90% of V
DD
—
—
ppm/V
Control Voltage Linearity
4
Modulation Bandwidth
V
C
Input Impedance
Nominal Control Voltage
Control Voltage Tuning Range
L
VC
BW
Z
VC
V
CNOM
V
C
BSL
Incremental
–5
–10
9.3
500
+5
+10
10.7
—
—
V
DD
%
kHz
kΩ
V
V
@ f
O
—
0
Notes:
1.
Positive slope; selectable option by part number. See "7. Ordering Information" on page 21.
2.
For best jitter and phase noise performance, always choose the smallest K
V
that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K
V
), Stability, and Absolute Pull Range (APR)” for more information.
3.
K
V
variation is ±10% of typical values.
4.
BSL determined from deviation from best straight line fit with V
C
ranging from 10 to 90% of V
DD
. Incremental slope
determined with V
C
ranging from 10 to 90% of V
DD
.
Rev. 0.31
5
FPGA/CPLD
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