74HC158
Quad 2-input multiplexer; inverting
Rev. 4 — 23 December 2015
Product data sheet
1. General description
The 74HC158 is a high-speed Si-gate CMOS device and is pin compatible with low power
Schottky TTL (LSTTL). The 74HC158 is specified in compliance with JEDEC
standard no. 7A.
The 74HC158 is a quad 2-input multiplexer which select 4 bits of data from two sources
and are controlled by a common data select input (S). The four outputs present the
selected data in the inverted form. The enable input (E) is active LOW.
When E is HIGH, all the outputs (1Y to 4Y) are forced HIGH regardless of all other input
conditions.
Moving the data from two groups of registers to four common output buses is a common
use of the 74HC158. The state of S determines the particular register from which the data
comes. It can also be used as a function generator.
The device is useful for implementing highly irregular logic by generating any four of the
16 different functions of two variables with one variable common.
The 74HC158 is the logic implementation of a 4-pole, 2-position switch, where the
position of the switch is determined by the logic levels applied to S.
The logic equations for the output are:
1Y = E.(1l1.S
1l0.S)
2Y = E.(2l1.S
2l0.S)
3Y = E.(3l1.S
3l0.S)
4Y = E.(4l1.S
4l0.S)
The 74HC158 is identical to the 74HC157 but has inverting outputs.
2. Features and benefits
Low-power dissipation
Inverting data path
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
−40°
C to +85
°C
and
−40 °C
to +125
°C
Nexperia
74HC158
Quad 2-input multiplexer; inverting
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC158D
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
Version
SOT109-1
Type number
4. Functional diagram
2
3
5
6
11 10 14 13
1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1
1 S
MULTIPLEXER
15 E
OUTPUTS
1Y
4
2Y
7
3Y
9
4Y
12
Fig 1.
Functional diagram
1
1
2
3
5
6
11
10
14
13
15
S
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
E
1Y
2Y
3Y
4Y
4
7
9
12
G1
EN
1
1
7
MUX
15
2
3
5
6
14
13
11
10
4
12
9
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC158
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 4 — 23 December 2015
©
2 of 16
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC158
Quad 2-input multiplexer; inverting
S
E
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
1Y
2Y
3Y
4Y
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
1
2
3
4
5
6
7
8
16 V
CC
15 E
14 4I0
13 4I1
12 4Y
11 3I0
10 3I1
9
3Y
Fig 5.
Pin configuration
74HC158
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 4 — 23 December 2015
©
3 of 16
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC158
Quad 2-input multiplexer; inverting
5.2 Pin description
Table 2.
Symbol
S
1I0
1I1
1Y
2I0
2I1
2Y
GND
3Y
3I1
3I0
4Y
4I1
4I0
E
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
common data select input
data input 1 from source 0
data input 1 from source 1
multiplexer output 1
data input 2 from source 0
data input 2 from source 1
multiplexer output 2
ground (0 V)
multiplexer output 3
data input 3 from source 1
data input 3 from source 0
multiplexer output 4
data input 4 from source 1
data input 4 from source 0
enable input (active LOW)
positive supply voltage
6. Functional description
6.1 Function table
Table 3.
Control
E
H
L
S
X
L
H
Function
[1]
Input
nI0
X
L
H
X
X
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Output
nl1
X
X
X
L
H
nY
H
H
L
H
L
74HC158
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 4 — 23 December 2015
©
4 of 16
Nexperia B.V. 2017. All rights reserved
Nexperia
74HC158
Quad 2-input multiplexer; inverting
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
SO16 package
[1]
Above 70
C:
P
tot
derates linearly with 8 mW/K.
[1]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
-
Max
+7
20
20
25
+50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and
fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
Typ
5.0
-
-
-
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Unit
V
V
V
C
ns/V
ns/V
ns/V
74HC158
All information provided in this document is subject to legal disclaimers.
.
Product data sheet
Rev. 4 — 23 December 2015
©
5 of 16
Nexperia B.V. 2017. All rights reserved
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