74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 03 — 23 December 2005
Product data sheet
1. General description
The 74HC138; 74HCT138 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL).
The 74HC138; 74HCT138 decoder accepts three binary weighted address inputs (A0, A1
and A3) and when enabled, provides 8 mutually exclusive active LOW outputs (Y0 to Y7).
The 74HC138; 74HCT138 features three enable inputs: two active LOW (E1 and E2) and
one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is
HIGH.
This multiple enable function allows easy parallel expansion of the 74HC138; 74HCT138
to a 1-of-32 (5 lines to 32 lines) decoder with just four 74HC138; 74HCT138 ICs and one
inverter.
The 74HC138; 74HCT138 can be used as an eight output demultiplexer by using one of
the active LOW enable inputs as the data input and the remaining enable inputs as
strobes. Not used enable inputs must be permanently tied to their appropriate active
HIGH- or LOW-state.
The 74HC138; 74HCT138 is identical to the 74HC238; 74HCT238 but has inverting
outputs.
2. Features
s
s
s
s
s
s
Demultiplexing capability
Multiple input enable for easy expansion
Complies with JEDEC standard no. 7A
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
x
HBM EIA/JESD22-A114-C exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
s
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
Philips Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Symbol Parameter
74HC138
t
PHL
,
t
PLH
propagation delay
An to Yn
E3 to Yn
En to Yn
C
i
C
PD
input capacitance
power dissipation
capacitance
propagation delay
An to Yn
E3 to Yn
En to Yn
C
i
C
PD
[1]
Conditions
V
CC
= 5 V; C
L
= 15 pF
Min
Typ
Max
Unit
-
-
-
-
V
I
= GND to V
CC
[1]
12
14
14
3.5
67
-
-
-
-
-
ns
ns
ns
pF
pF
-
74HCT138
t
PHL
,
t
PLH
V
CC
= 5 V; C
L
= 15 pF
-
-
-
-
V
I
= GND to (V
CC
−
1.5 V)
[1]
17
19
19
3.5
67
-
-
-
-
-
ns
ns
ns
pF
pF
input capacitance
power dissipation
capacitance
-
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74HC138
74HC138N
74HC138D
74HC138DB
74HC138PW
74HC138BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP16
SO16
SSOP16
TSSOP16
plastic dual in-line package; 16 leads (300 mil);
long body
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
SOT38-1
SOT109-1
SOT338-1
SOT403-1
Description
Version
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads;
16 terminals; body 2.5
×
3.5
×
0.85 mm
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
74HC_HCT138_3
Product data sheet
Rev. 03 — 23 December 2005
2 of 23
Philips Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Table 2:
Ordering information
…continued
Package
Temperature range Name
Description
plastic dual in-line package; 16 leads (300 mil);
long body
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT38-1
SOT109-1
SOT338-1
SOT403-1
Type number
74HCT138
74HCT138N
74 HCT138D
74HCT138DB
74HCT138PW
74HCT138BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
DIP16
SO16
SSOP16
TSSOP16
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads;
16 terminals; body 2.5
×
3.5
×
0.85 mm
5. Functional diagram
Y0
1
1
2
3
A0
A1
A2
Y0
Y1
Y2
Y3
4
5
6
E1
E2
E3
Y4
Y5
Y6
Y7
mna370
15
14
13
12
11
10
9
7
A0
A1
A2
3-to-8
DECODER
ENABLE
EXITING
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
2
3
4
5
6
E1
E2
E3
mna372
Fig 1. Logic symbol
Fig 2. Functional diagram
74HC_HCT138_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 23 December 2005
3 of 23
Philips Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
A2
Y7
Y6
A1
Y5
A0
Y4
E1
Y3
E2
Y2
E3
Y1
Y0
001aae059
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
74HC138BQ
74HCT138BQ
terminal 1
index area
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
001aae061
A0
A1
A2
E1
E2
E3
Y7
GND
1
2
3
4
5
6
7
8
A1
A2
E1
E2
E3
Y7
2
3
4
5
6
7
8
GND
Y6
9
GND
(1)
16 V
CC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
1
A0
74HC138
74HCT138
001aae060
Transparent top view
Y6
(1) The die substrate is attached to this
pad using conductive die attach
material. It can not be used as supply
pin or input.
Fig 4. Pin configuration DIP16, SO16,
SSOP16 and TSSOP16
Fig 5. Pin configuration DHVQFN16
74HC_HCT138_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 23 December 2005
4 of 23
Philips Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
6.2 Pin description
Table 3:
Symbol
A0
A1
A2
E1
E2
E3
Y7
GND
Y6
Y5
Y4
Y3
Y2
Y1
Y0
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
address input 0
address input 1
address input 2
enable input 1 (active LOW)
enable input 2 (active LOW)
enable input 3 (active HIGH)
output 7 (active LOW)
ground (0 V)
output 6 (active LOW)
output 5 (active LOW)
output 4 (active LOW)
output 3 (active LOW)
output 2 (active LOW)
output 1 (active LOW)
output 0 (active LOW)
positive supply voltage
7. Functional description
Table 4:
Control
E1
H
X
X
L
E2
X
H
X
L
E3
X
X
L
H
L
L
L
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Function table
[1]
Input
A2
X
A1
X
A0
X
Output
Y7
H
Y6
H
Y5
H
Y4
H
Y3
H
Y2
H
Y1
H
Y0
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
74HC_HCT138_3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 23 December 2005
5 of 23
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