74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Rev. 5 — 26 January 2015
Product data sheet
1. General description
The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2)
to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs
(E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines)
decoder with just four ‘138’ ICs and one inverter. The ‘138’ can be used as an eight output
demultiplexer by using one of the active LOW enable inputs as the data input and the
remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC138: CMOS level
For 74HCT138: TTL level
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC138N
74HCT138N
74HC138D
74 HCT138D
74HC138DB
74HCT138DB
40 C
to +125
C
SSOP16
40 C
to +125
C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT109-1
SOT338-1
40 C
to +125
C
Name
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number
NXP Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
Table 1.
Ordering information
…continued
Package
Temperature range
Name
TSSOP16
Description
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT403-1
40 C
to +125
C
40 C
to +125
C
Type number
74HC138PW
74HCT138PW
74HC138BQ
74HCT138BQ
DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1
very thin quad flat package; no leads;
16 terminals; body 2.5
3.5
0.85 mm
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
Functional diagram
Fig 3.
Logic diagram
74HC_HCT138
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 26 January 2015
2 of 19
NXP Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration DIP16, SO16, SSOP16 and
TSSOP16
Fig 5.
Pin configuration DHVQFN16
5.2 Pin description
Table 2.
Symbol
A0, A1, A2
E1, E2
E3
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7
GND
V
CC
Pin description
Pin
1, 2, 3
4, 5
6
15, 14, 13, 12, 11, 10, 9, 7
8
16
Description
address input A0, A1, A2
enable input E1, E2 (active LOW)
enable input E3 (active HIGH)
output Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 (active LOW)
ground (0 V)
positive supply voltage
74HC_HCT138
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 26 January 2015
3 of 19
NXP Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
6. Functional description
Table 3.
Control
E1
H
X
X
L
E2
X
H
X
L
E3
X
X
L
H
L
L
L
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Function table
[1]
Input
A2
X
A1
X
A0
X
Output
Y7
H
Y6
H
Y5
H
Y4
H
Y3
H
Y2
H
Y1
H
Y0
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
quiescent supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16 package
SSOP16 package
TSSOP16 package
DHVQFN16 package
[1]
[2]
[3]
[4]
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
[1]
[2]
[3]
[3]
[4]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
-
-
-
-
-
Max
+7
20
20
25
50
50
+150
750
500
500
500
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
mW
mW
mW
74HC_HCT138
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 26 January 2015
4 of 19
NXP Semiconductors
74HC138; 74HCT138
3-to-8 line decoder/demultiplexer; inverting
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
t/V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Conditions
Min
2.0
0
0
40
-
-
-
74HC138
Typ
5.0
-
-
+25
-
1.67
-
Max
6.0
V
CC
V
CC
+125
625
139
83
Min
4.5
0
0
40
-
-
-
74HCT138
Typ
5.0
-
-
+25
-
1.67
-
Max
5.5
V
CC
V
CC
+125
-
139
-
V
V
V
C
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
T
amb
= 25
C
Min
74HC138
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
input leakage
current
supply current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
0.1
0.1
0.1
0.26
0.26
0.1
8.0
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1.0
80
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
160
V
V
V
V
V
A
A
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Typ
Max
T
amb
=
40 C
to
+85
C
Min
Max
T
amb
=
40 C
to Unit
+125
C
Min
Max
74HC_HCT138
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 5 — 26 January 2015
5 of 19
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