D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MRFIC1502/D
The MRFIC Line
Integrated GPS Downconverter
This integrated circuit is intended for GPS receiver applications. The dual
conversion design is implemented in Motorola’s low–cost high performance
MOSAIC 3 silicon bipolar process and is packaged in a low–cost surface mount
TQFP–48 package. In addition to the mixers, a VCO, a PLL and a loop filter are
integrated on–chip. Output IF is nominally 9.5 MHz.
•
65 dB Minimum Conversion Gain
•
5 Volts Operation
•
50 mA Typical Current Consumption
•
Low–Cost, Low Profile Plastic LQFP Package
•
Order MRFIC1502R2 for Tape and Reel.
R2 Suffix = 1,500 Units per 16 mm, 13 inch Reel.
•
Device Marking = M1502
MRFIC1502
1.575 GHz GPS
DOWNCONVERTER
CASE 932–02
(LQFP–48)
GND
48
GND
VCO VT
GND
VCC5
GND
VCO CE
GND
SF CAP1
GND
1
2
3
4
5
6
7
8
9
GND
47
GND
46
GND
45
RF IN GND VCC1 GND
44
43
42
41
TO
BPF
40
FROM
BPF GND
39
38
GND
37
36
35
34
33
GND
38 MHz TRAP
38 MHz TRAP
BYPASS CAP
IF OUT
VCC2
GND
TQFP–48
ACTIVE
FILTER
VCO
40
2
32
31
30
29 GAIN CONTROL
LOOP
FILTER
28 VCC3
27 GND
26 GND
25 GND
13
C2A
14
C2B
15
C1
16
CA
17
CB
18
DCX0
19
20
21
CLK
OUT
22
GND
23
GND
24
GND
PHASE
DETECTOR
SF CAP2 10
GND 11
GND 12
VCC4 GND
Pin Connections and Functional Block Diagram
MOTOROLA WIRELESS SEMICONDUCTOR
©
Motorola, Inc. 2001
SOLUTIONS DEVICE DATA
Rev 1
MRFIC1502
1
MAXIMUM RATINGS
Rating
DC Supply Voltage
DC Supply Current
Operating Ambient Temperature
Storage Temperature Range
Lead Soldering Temperature Range (10 seconds)
Symbol
VDD
IDD
TA
Tstg
—
Limit
+6.0
60
– 40 to + 100
– 65 to +150
+260
Unit
Vdc
mA
°C
°C
°C
ELECTRICAL CHARACTERISTICS
(TA = 25°C, and VCC = 5 V, Tested in Circuit shown in Figure 1 unless otherwise noted)
Characteristic
Supply Voltage
Supply Current
L–Band Gain (Measured from L–Band Input to 47 MHz Output)
IF Gain (Measured from 47 MHz Input to 9.5 MHz Output with Gain
Control at Maximum)
Conversion Gain (Measured from L–Band Input to 9.5 MHz Output with
Gain Control at Maximum)
Gain Control (Externally Adjustable 0 to 5.0 V, Maximum at 0 V)
Noise Figure (Double Sideband)
L–Band Input VSWR (Measured into 50
Ω;
1575.42
±
5.0 MHz)
First IF Output VSWR (Measured into 50
Ω;
47.74
±
5.0 MHz)
Second IF Output VSWR (Measured into 50
Ω;
9.5
±
5.0 MHz)
Input Impedance @ 1st IF 47.7
±
5 MHz (For Reference Only)
Output 1.0 dB Compression Point
First LO (Measured at the First IF Output)
All Other Harmonics (Measured at the First IF Output)
38.1915 MHz Leakage at First IF Output
Second LO (Measured at the Second IF Output)
All Other Harmonics (Measured at Second IF Output)
Reference Oscillator Input
Clock Output
Frequency
Amplitude
Low
HIgh
(Clock Amplitude Measured with the Output Loaded in 15 pF and 40 kΩ)
Duty Cycle
VCO Lock Voltage
Phase Detector Gain
VCO Modulation Sensitivity
Min
4.75
—
—
—
65
—
—
—
—
—
—
—
—
—
—
—
—
400
2Xfref
Typ
—
—
20
45
—
40
9.5
2:1
2:1
2:1
2000
–7
–20
–45
–50
–25
–45
—
—
Max
5.25
60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4500
2Xfref
Unit
Vdc
mA
dB
dB
dB
dB
dB
—
—
—
Ω
dBm
dBm
dBm
dBm
dBm
dBm
mVpp
—
2.0
45
1.2
—
—
—
0.16
15
0.8
—
55
3.0
—
—
V
V
%
V
V/Radian
MHz/V
MRFIC1502
2
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
Table 1. Port Impedance Derived from Circuit Characterization
Zin
Ohms
R
38.3
54.45
43
560
jX
–16.09
11.3
1.5
–850
Pin Number
44
40
39
32
Pin Name
RF IN
TO BPF
FROM BPF
IF OUT
f
(MHz)
1575.42
47.74
47.74
9.5
Zin represents the input impedance of the pin.
APPLICATION INFORMATION
Design Philosophy
The MRFIC1502 design is a standard dual downconver-
sion configuration with an integrated fixed frequency phase–
locked loop to generate the two local oscillators and the
buffer to generate the sampling clock for a digital correlator
and decimator. The active device for the L–band VCO is also
integrated on the chip. This chip is designed in the third gen-
eration of Motorola’s Oxide Self Aligned Integrated Circuits
(MOSAIC 3) silicon bipolar process.
Circuit Considerations
The RF input to the MRFIC1502 is internally matched to 50
ohms. Therefore, only AC coupling is required on the input.
The output of the amplifier is fed directly into the first mixer.
This mixer is an active Gilbert Cell configuration. The output
of the mixer is brought off–chip for filtering of the unwanted
mixer products. The amplifier and mixer have their own VCC
supply (pin 42) in order to reduce the amount of coupling to
the other circuits. There are two bypass capacitors on this
pin, one for the high frequency components and one for the
lower frequency components. These two capacitors should
be placed physically as close to the bias pin as possible to
reduce the inductance in the path. The capacitors should
also be grounded as close to the ground of the IC as pos-
sible, preferably through a ground plane.
The output impedance of the first mixer is 50 ohms, while
the input impedance to the first IF amplifier is 1 kΩ. There is
a trap (zero) designed in at the second LO frequency to limit
the amount of LO leakage into the high gain first IF amplifier.
The first IF amplifier is a variable gain amplifier with 25 dB
of gain and 40 dB of gain control. The gain control pin can be
grounded to provide the maximum gain out of the amplifier. If
the baseband design utilizes a multi–bit A/D converter in the
digital signal processing chip, this amplifier could be used to
control the input to the A/D converter. The amplifier has an
external bypassing capacitor. This capacitor should be on
the order of 0.01
µF,
and again should be located near the
package pin.
The second mixer design is also a Gilbert Cell
configuration. The interface between the mixer and the
second IF amplifier is differential in order to increase noise
immunity. This differential interface is also brought off–chip
so that some additional filtering could be added in parallel
between the output of the mixer and input to the amplifier.
This filtering is primarily to reduce the amount of LO leakage
into the final IF amplifier and is achieved using a single 3.9
pF capacitor across the differential ports. The value of the
capacitor determines the high frequency of the low pass
structure.
The supply pin for the IF circuits is pin 33. This supply pin
should be isolated from the other chip supplies in order to re-
duce the amount of coupling. The recommended capacitors
are a 47 pF and a 0.01
µF,
in parallel to bypass the supply to
ground and should be placed physically as close to the pin as
possible.
The output of the second IF amplifier is 50 ohms with a
bandwidth of
±5.0
MHz. This signal must be filtered before
being digitized in order to limit the noise entering the A/D
converter.
VCO Resonator Design
The design and layout of the circuits around the voltage
controlled oscillator (VCO) are the most sensitive of the en-
tire layout. The active device and biasing resistors are inte-
grated on the MRFIC1502. The external circuits consist of
the power supply decoupling, the capacitors for the inte-
grated supply superfilter, the resonator and frequency adjust-
ing elements, and the bypassing capacitor on the emitter of
the active device.
The VCO supply is isolated from the rest of the PLL circuits
in order to reduce the amount of noise that could cause fre-
quency/phase noise in the VCO. The supply should be fil-
tered using a 22
µH
inductor in series and a 27 pF and 0.01
µF
in parallel. The 27 pF capacitor should be series resonant
at least as high as the VCO frequency to get the most L–
band bypassing as possible. The on–chip supply filter re-
quires two capacitors off–chip to filter the supply. The
capacitors on the input (pin 8) and output (pin 10) of the filter
are 1.0
µF,
and the output also has a high frequency bypass
capacitor in parallel. The input capacitor should not be smaller
than a 1.0
µF
to insure stability of the supply filter.
The VCO design is a standard negative resistance cell
with a buffer amplifier. The resonating structure is connected
to the base of the active device and consists of a coupling
capacitor, a hyper–abrupt varactor diode, and a wire wound
chip inductor. With the values shown on the application
MRFIC1502
4
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
