622 Mbit/s
MUX/DeMUX
Chip Set
GD16131/GD16132
General Description
The GD16131, 32:4 / Quad 8:1 MUX and
the GD16132, 4:32 / Quad 1:8 DeMUX
are intended for use in 2.5 Gbit/s trans-
mission systems. The high-speed inter-
face is designed to accommodate the
requirements of the GD16554 (4:1 MUX)
and the GD16543 (1:4 DeMUX) both
meeting CCITT specifications at
2.5 Gbit/s SDH STM-16. The GD16131
and GD16162 take care of the interface
between the high-speed devices differen-
tial ECL level I/O’s at 622 Mbit/s and
lower speed CMOS gate arrays at
78 Mbit/s. Hence they are dual supply
devices shifting levels between true ECL
and TTL.
The GD16131 and GD16132 are made
as four identical blocks of 8 bit and a
clock driver circuit. The 8 bit blocks are
implemented as shift registers to obtain
the best speed/power ratio of the process
technology used. Also this means easy
clock distribution with small delay be-
tween incoming and outgoing signals.
For the GD16131 the 622 Mbit/s data
outputs are re-timed at the chip edge to
cut down delay from clock-in to data-out,
allowing counter directional clocking.
Thus the on-chip delay, except output
buffer load dependant delay, is kept be-
low 1 ns. A 622 MHz output clock with
close timing relation to the data outputs
also allows co-directional clocking. On
both MUX and DeMUX, the subdivided
78 MHz clock are also re-timed at the
chip edge to cut down delay from the
622 MHz input clock. The phase relation
between low-speed data and the subdi-
vided output clock are selectable in four
phases.
The GD16131 and GD16132 are pack-
aged in 68 pin Multi Layer Ceramic
(MLC) packages, yielding excellent high-
speed signal accommodation and ther-
mal conditions. The chip set is designed
for an operating temperature between
–5
°C
and +85
°C,
case temperature.
With power consumption of 1.3 W typical
for both GD16131 and GD16132, only
little or no heat sink is required.
Bit naming convention
Naming of pins on parallel ports is made
assuming the transfer bit order to be in-
creasing starting with position D0, D1, ...,
D31.
Features
GD16131
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Quad 8:1 MUX
All high-speed I/O’s are differential,
ECL level.
All low-speed I/O’s are TTL level,
outputs drive 10 pF at 78 MHz.
Subdivided output clock to data rela-
tion selectable in four phases.
Dual supply: +5 V, -5.2 V.
68 pin MLC flat package.
High-speed pins on single side of
package for easy PCB routing.
Power consumption: 1.3 W typical.
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GD16132
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Quad 1:8 DeMUX
All high-speed I/O’s are differential,
ECL level.
All low-speed I/O’s are TTL level,
outputs drive 10 pF at 78 MHz.
Subdivided output clock to data
relation selectable in four phases.
Dual supply: +5 V, -5.2 V.
68 pin MLC flat package.
High-speed pins on single side of
package for easy PCB routing.
Power consumption: 1.3 W typical.
l
D0
D4
:
D24
D28
D1
D5
:
D25
D29
D2
D6
:
D26
D30
D3
D7
:
D27
D31
D0
D4
:
D24
D28
D1
D5
:
D25
D29
D2
D6
:
D26
D30
D3
D7
:
D27
D31
VEE
VDD
VCC
CKIP
CKIN
SEL1
SEL2
RESET
DO0P
DO0N
DI0P
DI0N
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DO1P
DO1N
DI1P
DI1N
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DO2P
DO2N
DI2P
DI2N
DO3P
DO3N
VTT
VEE
VDD
VCC
DI3P
DI3N
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CKOP
CKON
CKIP
CKIN
SEL1
SEL2
RESET
Clock
Generator
CKOUT
Clock
Generator
CKOUT
Data Sheet Rev.: 12
Function Description
GD16131 - MUX
The first bit shifted out is the one with the lowest number.
The first internal 8:1 MUX of the GD16131 services bits
0-4-8-12-16-20-24-28. Neighboring input pins in the pin-out go
to the same MUX.
GD16132 - DeMUX
The first bit received is shifted out on the lowest pin number.
The first of the 4 internal 1:8 DeMUX of the GD16132 drives
outputs 0-4-8-12-16-20- 24-28. Neighboring output pins go to
the same DeMUX.
Pin List – GD16131
Mnemonic:
D0 .. D31
Pin No.:
22, 32, 56, 66, 23,
33, 54, 64, 24, 36,
53, 63, 25, 37, 50,
62, 27, 39, 49, 61,
28, 40, 47, 59, 29,
41, 46, 58, 30, 42,
45, 57
10, 11
7, 8
5, 6
2, 3
12, 13
15, 16
44
19, 20
Pin Type:
TTL IN
Description:
Parallel data input port to MUX.
DO0P, DO0N
DO1P, DO1N
DO2P, DO2N
DO3P, DO3N
CKIP, CKIN
CKOP, CKON
CKOUT
SEL1, SEL2
ECL OUT
Differential serial data outputs from MUX.
ECL IN
ECL OUT
TTL OUT
TTL IN
Differential clock input, 622 MHz.
Differential clock output with timing related to data outputs,
622 MHz.
Subdivided output clock, 78 MHz. Maximum load 10 pF.
CKOUT clock phase select:
SEL2 SEL1
0
0
T
DEL
= 0°
0
1
T
DEL
= 270° (-90)°
1
0
T
DEL
= 180°
1
1
T
DEL
= 90°
Test reset. Not needed on power up, the device is self synchro-
nising. Reset is used for test only.
0 V power for core and ECL I/O.
RESET
VDD
67
4, 9, 14, 21, 26, 31,
38, 43, 48, 55, 60,
65
18, 52
1, 34, 51
17, 35, 68
TTL IN
PWR
VCC
VEE
NC
PWR
PWR
+5 V power for core and TTL I/O. All power pins must be
connected. Decoupling should be made close to package body.
-5.2 V power for core and ECL I/O. All power pins must be
connected. Decoupling should be made close to package body .
Not Connected
Data Sheet Rev.: 12
GD16131/GD16132
Page 2 of 11
Pin List – GD16132
Mnemonic:
D0 .. D31
Pin No.:
29, 41, 45, 57, 28,
40, 46, 58, 27, 39,
47, 59, 25, 37, 49,
61, 24, 36, 50, 62,
23, 33, 53, 63, 22,
32, 54, 64, 20, 30,
56, 66
10, 11
12, 13
2, 3
5, 6
7, 8
42
16, 15
Pin Type:
TTL OUT
Description:
Parallel data output from DeMUX. Maximum load 10 pF.
DI0P, DI0N
DI1P, DI1N
DI2P, DI2N
DI3P, DI3N
CKIP, CKIN
CKOUT
SEL1, SEL2
ECL IN
Differential serial data inputs.
ECL IN
TTL OUT
TTL IN
Differential clock input, 622 MHz.
Subdivided output clock, 78 MHz. Maximum load 10 pF.
CKOUT clock phase select:
SEL2 SEL1
0
0
T
DEL
= 0°
0
1
T
DEL
= 270° (-90)°
1
0
T
DEL
= 180°
1
1
T
DEL
= 90°
Test reset. Not needed on power up, the device is self synchro-
nising. Reset is used for test only.
0 V power for core and ECL I/O.
RESET
VDD
67
4, 9, 14, 21, 26, 31,
38, 43, 48, 55, 60,
65
1, 34, 35, 52, 68
17, 51
18, 19, 44
TTL IN
PWR
VCC
VEE
NC
PWR
PWR
+5 V power for core and TTL I/O. All power pins must be
connected. Decoupling should be made close to package body.
-5.2 V power for core and ECL I/O. All power pins must be
connected. Decoupling should be made close to package body.
Not Connected.
Data Sheet Rev.: 12
GD16131/GD16132
Page 3 of 11
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