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HCTS74D/SAMPLE

产品描述HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, SIDE BRAZED, CERAMIC, DIP-14
产品类别逻辑    逻辑   
文件大小143KB,共10页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 选型对比 全文预览

HCTS74D/SAMPLE概述

HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, SIDE BRAZED, CERAMIC, DIP-14

HCTS74D/SAMPLE规格参数

参数名称属性值
厂商名称Renesas(瑞萨电子)
零件包装代码DIP
包装说明DIP,
针数14
Reach Compliance Codeunknown
系列HCT
JESD-30 代码R-CDIP-T14
逻辑集成电路类型D FLIP-FLOP
位数1
功能数量2
端子数量14
输出极性COMPLEMENTARY
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码DIP
封装形状RECTANGULAR
封装形式IN-LINE
传播延迟(tpd)31 ns
认证状态Not Qualified
座面最大高度5.08 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
触发器类型POSITIVE EDGE
宽度7.62 mm

文档预览

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HCTS74MS
September 1995
Radiation Hardened Dual-D
Flip-Flop with Set and Reset
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-183S CDIP2-T14, LEAD FINISH C
TOP VIEW
R1 1
D1 2
CP1 3
S1 4
Q1 5
Q1 6
GND 7
14 VCC
13 R2
12 D2
11 CP2
10 S2
9 Q2
8 Q2
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
• Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
• Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
• Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
o
C to +125
o
C
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii
5µA at VOL, VOH
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-183S CDFP3-F14, LEAD FINISH C
TOP VIEW
R1
D1
CP1
S1
Q1
Q1
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
R2
D2
CP2
S2
Q2
Q2
Description
The Intersil HCTS74MS is a Radiation Hardened positive
edge triggered flip-flop with set and reset.
The HCTS74MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCTS74MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCTS74DMSR
HCTS74KMSR
HCTS74D/Sample
HCTS74K/Sample
HCTS74HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Spec Number
File Number
1
518626
2143.2

HCTS74D/SAMPLE相似产品对比

HCTS74D/SAMPLE HCTS74K/SAMPLE
描述 HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, SIDE BRAZED, CERAMIC, DIP-14 HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14
厂商名称 Renesas(瑞萨电子) Renesas(瑞萨电子)
零件包装代码 DIP DFP
包装说明 DIP, DFP,
针数 14 14
Reach Compliance Code unknown unknow
系列 HCT HCT
JESD-30 代码 R-CDIP-T14 R-CDFP-F14
逻辑集成电路类型 D FLIP-FLOP D FLIP-FLOP
位数 1 1
功能数量 2 2
端子数量 14 14
输出极性 COMPLEMENTARY COMPLEMENTARY
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装代码 DIP DFP
封装形状 RECTANGULAR RECTANGULAR
封装形式 IN-LINE FLATPACK
传播延迟(tpd) 31 ns 31 ns
认证状态 Not Qualified Not Qualified
座面最大高度 5.08 mm 2.92 mm
最大供电电压 (Vsup) 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V
表面贴装 NO YES
技术 CMOS CMOS
端子形式 THROUGH-HOLE FLAT
端子节距 2.54 mm 1.27 mm
端子位置 DUAL DUAL
触发器类型 POSITIVE EDGE POSITIVE EDGE
宽度 7.62 mm 6.285 mm

 
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