CAT24C21
1-kb Dual Mode Serial EEPROM for VESA™ "Plug-and-Play"
FEATURES
s
DDC1
TM
/DDC2
TM
interface compliant for
s
Low power CMOS technology
s
1,000,000 program/erase cycles
s
100 year data retention
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
monitor identification
s
400 kHz I C bus compatible*
s
2.5 to 5.5 volt operation
s
16-byte page write buffer
s
Hardware write protect
2
s
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
packages
s
Industrial temperature range
DESCRIPTION
The CAT24C21 is a 1-kb Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. The
device complies with the Video Electronics Standard
Association's (VESA™), Display Data Channel (DDC™)
standards for "Plug-and-Play" monitors. The "transmit-
only" mode (DDC1™) is controlled by the VCLK clock
input and the "bi-directional" mode (DDC2™) is controlled
by the SCL clock input, with both modes sharing a
common SDA input/output (I/O). The transmit-only mode
is a read-only mode, while the bi-directional mode is a
read and write mode following the I
2
C protocol. In write
mode the CAT24C21 features a 16-byte page write
buffer. The device is available in 8-in DIP, SOIC, TSSOP,
MSOP and TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
FUNCTIONAL SYMBOL
SOIC Package (J, W)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
SCL
VCC
CAT24C21
SDA
MSOP Package (R, Z)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
TDFN Package (RD4, ZD4)
VCLK
NC
1
NC
2
NC
3
VSS
4
8
VCC
7
VCLK
6
SCL
5
SDA
VSS
3 mm x 3 mm
Top View
PIN FUNCTIONS
Pin Name
NC
SDA
SCL
VCLK
V
CC
Function
No Connect
Serial Data/Address
Serial Clock (bi-directional mode)
Serial Clock (transmit-only mode)
Power Supply
Ground
TSSOP Package (U, Y)
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus
Protocol.
V
SS
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1032, Rev. N
CAT24C21
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
............ -2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground .............. -2.0 V to +7.0 V
Package Power Dissipation
Capability (T
A
= 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current
(2)
....................... 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)(*)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Units
Program/Erase Cycles
Years
Volts
mA
(*) Page Mode, V
CC
= 5 V, 25˚C
D.C. OPERATING CHARACTERISTICS
V
CC
= 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range.
Symbol
I
CC
I
SB(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
IL
V
IH
Parameter
Power Supply Current
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Input Low Voltage (VCLK)
Input High Voltage (VCLK)
Test Conditions
f
SCL
= 400 kHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
Min
Max
2
0
10
10
Units
mA
µA
µA
µA
V
V
V
V
V
–1
V
CC
x 0.7
V
CC
= 3.0 V, I
OL
= 3 mA
V
CC
≥
2.7 V
2.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.8
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V
Symbol
C
I/O(3)
C
IN(3)
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (VCLK, SCL)
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Min
Max
8
6
Units
pF
pF
Note:
(1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
(2) Output shorted for no more than one second.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from –1 V to V
CC
+ 1 V.
(5) Standby Current, I
SB
= 0
µA
(<900 nA).
Doc. No. 1032, Rev. N
2
CAT24C21
A.C. CHARACTERISTICS
V
CC
= 2.5 V to 5.5 V, unless otherwise specified. Industrial temperature range.
Symbol
Parameter
Min
Max
Units
Transmit-only Mode
T
VAA
T
VHIGH
T
VLOW
T
VHZ
T
VPU
Output valid from VCLK
VCLK high
VCLK low
Mode transition
Transmit-only power-up
0
0.6
1.3
0.5
0.5
µs
µs
µs
µs
ns
Read & Write Cycle Limits
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time Constant at SCL,
SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New
Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
100
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
400
100
1
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing
(1)(2)
t
PUR
t
PUW
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
Write Cycle Limits
t
WR
Write Cycle Time
5
ms
The write cycle time is the time from a valid stop condition
of a write sequence to the end of the internal program/
erase cycle. During the write cycle, the bus interface
circuits are disabled, SDA is allowed to remain high, and
the device does not respond to its slave address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
3
Doc. No. 1032, Rev. N
CAT24C21
PIN DESCRIPTION
The SCL serial clock input pin is used to clock all data
transfers into or out of the device when in the
bi-directional mode.
The SDA bi-directional serial data/address pin is used to
transfer data into and out of the device. The SDA pin is
an open drain output and can be wire-ORed with other
open drain or open collector outputs.
TRANSMIT-ONLY MODE: (DDC1)
Upon power-up, the CAT24C21 will output valid data
only after it has been initialized. During initialization,
data will not be available until after the first nine clocks
are sent to the device (Figure 2). The starting address for
the transmit-only mode can be determined during
initialization. If the SDA pin is high during the first eight
clocks, the starting address will be 7FH. If the SDA pin
is low during the first eight clocks, the starting address
will be 00H. During the ninth clock, SDA will be in the high
impedance state.
Data is transmitted in 8 bit words with the most significant
bit first, followed by a 9th 'don't care' bit which will be in
the high impedance state (Figure 3). The CAT24C21 will
continuously sequence through the entire memory array
as long as VCLK is present and no falling edges on SCL
are detected. When the maximum address (7FH) is
reached, addressing will wrap around to the zero location
(00H) and transmitting will continue. The bi-directional
mode clock (SCL) pin must be held high for the device
to remain in the transmit-only mode.
FUNCTIONAL DESCRIPTION
The CAT24C21 has two modes of operation: the transmit-
only mode and the bi-directional mode. There is a
separate 2-wire protocol to support each mode, each
having a separate clock input (VCLK and SCL
respectively) and both modes sharing a common bi-
directional data line (SDA). The CAT24C21 enters the
transmit-only mode upon power up and begins outputting
data on the SDA pin with each clock signal on the VCLK
pin. The device will remain in the transmit-only mode
until there is a valid HIGH to LOW transition on the SCL
pin, when it will switch to the bi-directional mode (Figure
1). Once in the bi-directinal mode, the only way to return
to the transmit-only mode is by powering down the
device.
The VCLK serial clock input pin is used to clock data out
of the device when in transmit-only mode. When held
low, in bi-directional mode, it will inhibit write operations.
Figure 1. Mode Transition
Transmit-Only Mode
SCL
TVHZ
Bi-Directional Mode
SDA
VCLK
Figure 2. Device Initialization for Transmit-only Mode
SCL
SDA
SDA at high impedance for 9 clock cycles
Bit8
Bit7
Bit6
Bit5
Bit4
VCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TVPU
TVAA
Doc. No. 1032, Rev. N
4
CAT24C21
BI-DIRECTIONAL MODE (DDC2)
The following defines the features of the I
2
C bus protocol
in bi-directional mode (Figure 4):
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
When in the bi-directional mode, all inputs to the VCLK
pin are ignored, except when a logic high is required to
enable write capability.
START Condition
The START condition (Figure 6) precedes all commands
to the device, and is defined as a HIGH to LOW transition
of SDA when SCL is HIGH. The CAT24C21 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24C21 (see Fig. 8). The next three
significant bits are "don't care". The last bit of the slave
address specifies whether a Read or Write operation is
to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write operation
is selected.
After the Master sends a START condition and the slave
address byte, the CAT24C21 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24C21 then performs a Read or Write operation
depending on the state of the R/W bit.
Figure 3. Transmit-only Mode
SCL must remain high for transmit-only mode
SCL
Bit8
(MSB)
Bit1
(LSB)
Don't
Care
SDA
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit8
Bit7
VCLK
TVHIGH
TVLOW
5
Doc. No. 1032, Rev. N
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