CAT24FC32A
32K-Bit Fast Mode I
2
C Serial CMOS EEPROM
FEATURES
■
Fast mode I
2
C bus compatible*
■
Max clock frequency:
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
■
Output slope control to eliminate ground
bounce
■
Zero standby current
■
Commercial temperature range
■
1,000,000 program/erase cycles
■
100 years data retention
■
8-pin PDIP, 8-pin SOIC (150 and 200 mil) and
400 kHz for V
CC
=1.8V to 3.6V
■
Hardware write protect for entire array
■
Cascadable for up to eight devices
■
32-Byte page or byte write modes
■
Self-timed write cycle with autoclear
■
5 ms max write cycle time
■
Random and sequential read modes
■
Schmitt trigger and spike suppression at SDA
8-pin TSSOP packages
■
"Green" package options available
and SCL inputs
DESCRIPTION
The CAT24FC32A is a 32K-bit Serial CMOS EEPROM
internally organized as 4Kx8 bits. The device is
compatible with Fast-mode I
2
C bus specification and
operates down to 1.8V with a bit rate up to 400 kbit/s.
Extended addressing capability allows up to 8 devices
to share the same bus. Catalyst's advanced CMOS
technology substantially reduces device power
requirements. The device is optimized for high
performance applications, where low power, low voltage
and high speed operation are required.
CAT24FC32A is available in 8-pin DIP, 8-pin SOIC
(JEDEC and EIAJ) and 8-pin TSSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
SENSE AMPS
SHIFT REGISTERS
TSSOP Package (U, Y)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
VCC
VSS
ACK
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
256
SDA
START/STOP
LOGIC
SOIC Package (J,W) (K, X)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
WP
CONTROL
LOGIC
XDEC
128
EEPROM
128 X 256
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1048, Rev. F
CAT24FC32A
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
Power Supply
Ground
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
1,000,000
100
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
RECOMMENDED OPERATING CONDITIONS
Temperature Range
Commercial
Minimum
0˚C
Maximum
+70˚C
Supply Voltage Range
1.8V to 3.6V
Device
CAT24FC32A
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
Doc. No. 1048, Rev. F
2
CAT24FC32A
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions, unless otherwise specified
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB(1)
V
IL(2)
V
IH(2)
V
OL1
V
OL2
Parameter
Input Leakage Current
(4)
Output Leakage Current
(4)
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Standby Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
-0.5
0.7V
CC
0
0.3V
CC
V
CC
+ 0.5
0.4
0.2V
CC
µA
V
V
V
V
2.5V
≤
V
CC
≤
3.6V
I
OL
= 3.0 mA
1.8V
≤
V
CC
< 2.5V
I
OL
= 3 mA
400
µA
Min.
-10
-10
Typ.
Max.
10
10
3
Units
µA
µA
mA
Test Conditions
V
IN
= GND to V
CC
V
IN
= GND to V
CC
f
SCL
= 400kHz
V
CC
= 3.6V
f
SCL
= 400kHz
V
CC
= 3.6V
V
CC
= 3.6V
V
IN
= GND or V
CC
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 3.6V
Symbol
C
I/O(3)
C
IN(3)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Max.
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Note:
(1) Standby current, I
SB
< 900 nA; A0, A1, A2, WP connected to GND; SCL, SDA = GND or VCC.
(2) V
IL
min and V
IH
max are reference values only and are not tested.
(3) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(4) I/O pins, SDA and SCL do not obstruct the bus lines if V
CC
is switched off.
3
Doc. No. 1048, Rev. F
CAT24FC32A
A.C. CHARACTERISTICS
Over recommended operating conditions, unless otherwise specified (Note 1).
VCC=1.8V - 3.6V
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R(2)
t
F(2)
t
HD:STA
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
SU:WP
t
HD:WP
t
AA
t
DH
t
BUF(2)
t
OF(2)
t
WC(3)
Parameter
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a
Repeated Start)
Data Input Hold Time
Data In Setup Time
Stop Condition Setup Time
WP Setup Time
WP Hold Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New
Transmission Can Start
Output Fall Time from V
IH
min to V
IL
max
Write Cycle Time (Byte or Page)
50
1.3
20
250
5
1.3
0.6
20
20
0.6
0.6
0
100
0.6
0
2.5
900
300
300
Min
Typ
Max
400
50
Units
kHz
ns
µs
µs
ns
ns
µs
µs
ns
ns
µs
µs
µs
ns
ns
µs
ns
ms
Power-Up Timing
(2)(4)
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Note:
(1) Test Conditions according to "AC Test Conditions" Table.
(2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
(4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 1048, Rev. F
4
CAT24FC32A
AC TEST CONDITIONS
Input pulse voltages
Input rise and fall times
Input reference voltages
Output reference voltages
Output load
0.2V
CC
to 0.8V
CC
≤
50 ns
0.3V
CC
, 0.7V
CC
0.5V
CC
Current source: I
OL
= 3mA;
CL: 400pF for f
SCl
max = 400kHz / 100pF for f
SCL
max = 1 MHz
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
SDA IN
tAA
SDA OUT
tDH
tBUF
Figure 2. WP Timing
2nd Byte Address
1
SCL
A7
A0
tSU:WP
Data
9
1
8
8
SDA
D7
D0
WP
tHD:WP
Figure 3. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5
Doc. No. 1048, Rev. F
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