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CD40193BMS

产品描述Binary Counter
产品类别逻辑    逻辑   
文件大小148KB,共12页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 选型对比 全文预览

CD40193BMS概述

Binary Counter

CD40193BMS规格参数

参数名称属性值
厂商名称Renesas(瑞萨电子)
包装说明,
Reach Compliance Codecompliant
逻辑集成电路类型BINARY COUNTER

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CD40192BMS
CD40193BMS
December 1992
CMOS Presettable Up/Down Counters
(Dual Clock With Reset)
Description
CD40192BMS Presettable BCD Up/Down Counter and the
CD40193BMS Presettable Binary Up/Down Counter each con-
sist of 4 synchronously clocked, gated “D” type flip-flops con-
nected as a counter. The inputs consist of 4 individual jam lines,
a PRESET ENABLE control, individual CLOCK UP and
CLOCK DOWN signals and a master RESET. Four buffered Q
signal outputs as well as CARRY and BORROW outputs for
multiple-stage counting schemes are provided.
The counter is cleared so that all outputs are in a low state by a
high on the RESET line. A RESET is accomplished asynchro-
nously with the clock. Each output is individually programmable
asynchronously with the clock to the level on the corresponding
jam input when the PRESET ENABLE control is low.
The counter counts up one count on the positive clock edge of
the CLOCK UP signal provided the CLOCK DOWN line is high.
The counter counts down one count on the positive clock edge
of the CLOCK DOWN signal provided the CLOCK UP line is
high.
The CARRY and BORROW signals are high when the counter
is counting up or down. The CARRY signal goes low one-half
clock cycle after the counter reaches its maximum count in the
count-up mode. The BORROW signal goes low one-half clock
cycle after the counter reaches its minimum count in the count-
down mode. Cascading of multiple packages is easily accom-
plished without the need for additional external circuitry by tying
the BORROW and CARRY outputs to the CLOCK DOWN and
CLOCK UP inputs, respectively, of the succeeding counter
package.
The CD40192BMS and CD40193BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
* CD40192B Only
Features
• CD40192BMS - BCD Type
• CD40193BMS - Binary Type
• High Voltage Type (20V Rating)
• Individual Clock Lines for Counting Up or Counting
Down
• Synchronous High-Speed Carry and Borrow Propaga-
tion Delays for Cascading
• Asynchronous Reset and Preset Capability
• Medium Speed Operation
- fCL = 8MHz (typ.) at 10V
• 5V, 10V and 15V Parametric Ratings
• Standardize Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Up/Down Difference Counting
• Multistage Ripple Counting
• Synchronous Frequency Dividers
• A/D and D/A Conversion
• Programmable Binary or BCD Counting
*H4W,
H1F
*H6P,
†H4X
†H6W
†CD40193B Only
Pinout
CD40192BMS, CD40193BMS
TOP VIEW
J2
Q2
Q1
1
2
3
16 VDD
15 J1
14 RESET
13 BORROW
12 CARRY
11 PRESET ENABLE
10 J3
9 J4
Functional Diagram
PRESET
ENABLE
J1
J2
J3
J4
CLOCK UP
CLOCK DOWN
15
1
10
9
5
4
11
3
2
6
7
13
12
CARRY
14
RESET
VDD = 16
VSS = 8
Q1
Q2
Q3
Q4
BORROW
CLOCK DOWN 4
CLOCK UP
Q3
Q4
VSS
5
6
7
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3363
7-1419

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