CD4094BC 8-Bit Shift Register/Latch with 3-STATE Outputs
October 1987
Revised April 2002
CD4094BC
8-Bit Shift Register/Latch with 3-STATE Outputs
General Description
The CD4094BC consists of an 8-bit shift register and a
3-STATE 8-bit latch. Data is shifted serially through the
shift register on the positive transition of the clock. The out-
put of the last stage (Q
S
) can be used to cascade several
devices. Data on the Q
S
output is transferred to a second
output, Q
′
S
, on the following negative clock edge.
The output of each stage of the shift register feeds a latch,
which latches data on the negative edge of the STROBE
input. When STROBE is HIGH, data propagates through
the latch to 3-STATE output gates. These gates are
enabled when OUTPUT ENABLE is taken HIGH.
Features
s
Wide supply voltage range:
s
Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
s
3-STATE outputs
3.0V to 18V
s
High noise immunity: 0.45 V
DD
(typ.)
Ordering Code:
Order Number
CD4094BCWM
CD4094BCN
Package Number
M16B
N16E
Package Description
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Top View
Truth Table
Clock
Output
Enable
Strobe
Data
Parallel Outputs
Q1
X
X
0
1
1
1
X
X
X
0
1
1
Hi-Z
Hi-Z
0
1
Q
N
Hi-Z
Hi-Z
Q
N
−
1
Q
N
−
1
Serial Outputs
Q
S
(Note 1)
Q7
No Change
Q7
Q7
Q7
Q
′
Σ
No Change
Q7
No Change
No Change
No Change
Q7
X
=
Don't Care
=
HIGH-to-LOW
=
LOW-to-HIGH
0
0
1
1
1
1
No Change No Change
No Change No Change No Change
Note 1:
At the positive clock edge, information in the 7th shift register stage is transferred to Q8 and Q
S
.
© 2002 Fairchild Semiconductor Corporation
DS005983
www.fairchildsemi.com
CD4094BC
Absolute Maximum Ratings
(Note 2)
(Note 3)
Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Storage Temperature Range (T
S
)
Power Dissipation (P
D
)
Dual-In-Line
Small Outline
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
°
C
700 mW
500 mW
Recommended Operating
Conditions
(Note 3)
DC Supply Voltage (V
DD
)
Input Voltage (V
IN
)
Operating Temperature Range (T
A
)
−
0.5 to
+
18 V
DC
−
0.5 to V
DD
+
0.5 V
DC
−
65
°
C to
+
150
°
C
+
3.0 to
+
15 V
DC
0 to V
DD
V
DC
−
55
°
C to
+
125
°
C
Note 2:
“Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
Note 3:
V
SS
=
0V unless otherwise specified.
DC Electrical Characteristics
(Note 3)
Symbol
I
DD
Quiescent
Device Current
V
OL
LOW Level
Output Voltage
V
OH
HIGH Level
Output Voltage
V
IL
LOW Level
Input Voltage
V
IH
HIGH Level
Input Voltage
I
OL
LOW Level
Output Current
(Note 4)
I
OH
HIGH Level
Output Current
(Note 4)
I
IN
I
OZ
Input Current
3-STATE Output
Leakage Current
Note 4:
I
OH
and I
OL
are tested one output at a time.
Parameter
Conditions
V
DD
=
5.0V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5.0V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5.0V
V
DD
=
10V
V
DD
=
15V
V
DD
=
5.0V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5.0V, V
O
=
0.5V or 4.5V
V
DD
=
10V, V
O
=
1.0V or 9.0V
V
DD
=
15V, V
O
=
1.5V or 13.5V
V
DD
=
5.0V, V
O
=
0.4V
V
DD
=
10V, V
O
=
0.5V
V
DD
=
15V, V
O
=
1.5V
V
DD
=
5.0V, V
O
=
4.6V
V
DD
=
10V, V
O
=
9.5V
V
DD
=
15V, V
O
=
13.5V
V
DD
=
15V, V
IN
=
0V
V
DD
=
15V, V
IN
=
15V
V
DD
=
15V, V
IN
=
0V or 15V
|I
O
|
≤
1
µA
|I
O
|
≤
1.0
µA
55°C
Min
Max
5.0
10
20
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
0.64
1.6
4.2
−0.64
−1.6
−4.2
−0.1
0.1
0.3
3.5
7.0
11.0
0.51
1.3
3.4
−0.51
−1.3
−3.4
4.95
9.95
14.95
Min
+25°C
Typ
Max
5.0
10
20
0
0
0
5.0
10.0
15.0
1.5
3.0
4.0
0.05
0.05
0.05
+125°C
Min
Max
150
300
600
0.05
0.05
0.05
4.95
9.95
14.95
1.5
3.0
4.0
3.5
7.0
11.0
Units
µA
V
V
V
V
0.88
2.25
8.8
0.88
2.25
8.8
−0.1
0.1
±0.3
0.36
0.9
2.4
−0.36
−0.9
−2.4
−1.0
1.0
±9
µA
µA
mA
mA
3
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