CD4066B Types
COS/MOS Quad Bilateral
Switch
For Transmission or Multiplexing of Analog or
Digital Signals
Features:
High-Voltage Types (20-Volt Rating)
The RCA-CD40668 IS a quad bilateral SWitch
Intended for the transmission or multiplex-
Ing of analog or digl tal Signals. It is pin-for·
pin compatible with RCA-CD40168, but
exhibits a much lower on-state resistance. In
addition, the on-state resistance IS relatively
constant over the full input-signal range.
The CD40668 consists of four independent
bilateral SWitches. A Single control Signal is
required per SWitch. 80th the p and the n
deVice in a given switch are biased on or
off simultaneously
by the control signal.
As shown in Fig_ 1, the well of the n-channel
deVice on each SWitch IS either tied to the
input when the switch is on or to VSS when
the switch IS off. This configuration elimi-
nates the variation of the SWitch-tranSistor
threshold voltage with input signal, and thus
keeps the on-state resistance low over the full
operating-signal range.
The advantages over Single-channel switches
include peak input-signal voltage swings equal
to the full supply Voltage, and more constant
on-state Impedance over the input-signal
range_ For sample-and-hold applications,
however, the CD40168 IS recommended.
The C04066B is available In 14-lead ceramic
dual-in-line packages (0 and F suffixes).
14-lead plastic dual-in-line packages (E suf-
fix). 14-lead ceramic flat pac;kages (K suffix).
and In chip form (H suffix).
•
15-V digital or ±7.5-V peak-to-peak switching
• 125n typical on-state resistance for 15-V operation
• Switch on-state resistance matched to within 5 n over
15-V signal-input range
• On-state resistance flat over full peak-to-peak signal
range
• High on/off output-voltage ratio: 80 dB typo
@
fis
=
10 kHz. R L
=
1 kn
• High degree of linearity: <0.5% distortion
FUNCTIONAL DIAGRAM
typo
@
fis
=
1 kHz, Vis
=
5 VP-P. VOO -
VSS
~
10 V, RL
=
10 kn
• Extremely lOw off-state swtch leakage
resulting in very low
offset
current and high
effective off-state resistance: 10 pA typo
@
Applications:
VOO - VSS
=
10 V, TA
=
25
0
C
• Analog signal switching/multiplexing
Signal gating
Modulator
• Extremely high control input impedan.;e
Squelch control
Demodulator
(control circuit isolated from signal cir-
Chopper
Commutating switch
cuit): 10 12 n typo
• Digital signal switching/Multiplexing
• Low crosstalk between switches: -50 dB
typo
@
fis
=
8 MHz, RL
=
1 kn
• Transmission-gate logic implementation
• Matched control-input to signal-output
• Analog-to-digital
&
digital-to-analog
capacitance: Reduces output signal
conversion
transients
• Digital control of frequency, impedance,
• Frequency response, switch on
=
40 MHz
phase, and analog-signal gain
(typ.)
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEOEC Tentative
Standard No.13A, "Standard Specifications
for Description of "B" Series CMOS Devices"
MAXIMUM
RATINGS,
Absolute-MaxImum Values
DC SUPPL Y-VOL TAGE RANGE. (VDD'
(Voltages referl!nced to VSS Termlnall
-05 to +20 V
INPUT VOLTAGE RANGE. ALL INPUTS
-05 to V DD +05 V
DC INPUT CURRENT. ANY ONE INPUT (except for
TRANSMIS~I.)N
GATE which IS 25 mAl
±10 mA
POWER DISSIPATION PoER PACKAGE (PO'
For T A : -40 to +60 C IPACKAGE TYPE E)
°
500mW
0
Derate Lln"_ '., at 12 mWI C to 200 mW
For T A : +60 to +85
~
(PACKAGE TYPE E)
(PACKAGE TYPES D. F)
For T A
=
-55 to +100
°
500mW
For T A: +100 to +125 C (PACKAGE TYPES D. F)
Derate Linearly at 12 mWI C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR TA
=
FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
100mW
OPERATING-TEMPERATURE RANGE (T A)
PACKAGE TYPES 0, F. H
-55 to +125°C
PACKAGE TYPE E
-40 to +85:C
STORAGE TEMPERATURE RANGE (T
st
I
-65 to +150 C
LEAD TEMPERATURE lOURING
SOLD~RINGI
At distance 1/16 ±
1/32
Inch 1159 ± 079 mml from case for 10 s max
f
NORMAL OPERATION
CONTROL-LINE BIASING
SWITCH ON.Vc"-·VDO
SWITCH OFF, VC -0' 'VSS
~~~E·p'SUBSTRATES
CONNECTED TO VDD
g
----
DO
'*ALL CONTROL INPUTS ARE
PROTECTEO BY
COSI
MOS
PROTECTION NETWORK
Vss
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that oper-
ation is always within the following ranges:
CHARACTERISTIC
Supply-Voltage Range (For T A
=
Full Package-
Temperature Range)
LIMITS
Min.
Max.
18
UNITS
FIg.
1 -
SchematIC dIagram of
1
of
4
identical
SWItches and its associated control
C/fCUltry.
3
V
218 ____________________________________________________________________________
II
CD4066B Types
ELECTRIC/'L CHARACTERISTICS
I.IMITS AT. INDICATED TEM-
PERATURES (OC)
~'alues
at -55, +25, +125 Apply
~o
D, F, H Packages
Values at -40, +25, +85 Apply to
E
Package
U
N
I
T
Characteristic
Test Conditions
S
+25
VIN VDD -
(V) (V) ·-55 -40 +85 f+125 Typ. Max.
0,5
5
0.25 025 7.5 7.5 0.01 0.25
QUiescent Device
Current,
0,10
0,15
0,20
Signal Inputs (Vis) and Output (Vos)
Vc = VOO
R L = 10 kU returned
to VOO - VSS
2
Vis = VSS to VOO
5
10
15
5
RL =lOkH, Vc = VOO
800
310
850
200 1300 470 1050
550 180
320 125
400
240
-
-
~
10
15
20
0.5
1
5
05
1
5
15
30
150
15 0.01
30 0.01
150 002
0.5
1
5
'no
IJ.A
INPUT SIGNAL VOLTAGE IVI.) -
V
92CS-21326Rl
Fig.
2-
Typical on-state resistance vs. input signal
voltage (all types).
On·State
Resistance. ron
Max.
,
~
:.i;!
300
~
250f--.-,+-___i--r+-..,
330 500
210
300
n
200
I
60n·State
Resistance
Between Any
I
2 SWitches, 6r on
Total Harmonic
Distortion.
THO
-3dB Cutolf
Frequency
(Switch on)
-50dB Feed·
through
Frequency
(Switch off)
i
Input/Output
'"
S
....
..
'?
.:::
~200~;~~~~~~~~~~~-q~~-+-~~~
150'~.~.~~~~~~~~~~~+--H~J~
-
-
-
-
-
10
15
_.
-
-
-
-
-
-
-
15
10
5
~ 100~:·~.:~~~-r~~~~~~~~+r~
n
-
-
%
I
SUPPLY VOLTAGE I
voo
VC=VOO
=
5 V, VSS=-5V. VIS(p-p)
-
= 5 V (SlOe wave centered on 0 V)
RL =10 kn, fls=l kHz slOe wave
VC=VOO=5V, VSS=-5V, VIS(p-p)
=5 V (Sine wave centered on 0 V
-
RL=lkn,
VC=VSS= -5V, VIS(p-p) = 5V
Sine wave centerd on
0
V
RL = 1 kn
-
-
0.4
-
-
-
40
-
MHz
-
VSS )
·15
I:!
V
i1\
;
-
-
-
-
1
-
MHz
1:
Vc = 0"
Leakage CJrrenl Vls=18V;Vos=
(Switch off)
o
V. VIS = OV;
lis Max.
Vos=18V
V~(AI
=VOO=
18
±0.1 ±0.1
±1
±1
±10·
5
±O 1 IJ.A
Ie
92CS-Z13URI
5
INPUT SIGNAL VOLTAGE IVI.) -
v
-50dB
Crosstalk
Frequency
+ V, VCVBI = VSS
= -5 V, islA) =
5 V
P_~'
50 n source
RL = 1 kn
RL=200kn
Vc = VOO.
VS~=
GNO.CL=50p
Vis = 10 V (Square
wave centered on 5 V
t r • tf
=
20 ns
VOO=+SV
Vc = VSS = -S V
5
10
15
-
-
-
-
8
-
MHz
Fig.
4-
Typical on-state resistance vs. Input signal
voltage (all types).
Propagation
Delay (Signal
Input to Signal
Output) tpd
Capacitancl!:
Input. Cis
Output. Cos
FeedthroL·gh.
Cios
-
-
-
-
-
-
-
20
10
40
20
15
ns
-
-
-
-
-
-
-
-
-
7
-
-
-
-
-
.-
-
-
8
8
O.S
-
-
-
tpF
INPUT SIGNAL VOLTAGE IV.. ) -
V
92CS-21HORI
Fig.
5-
on-state resistance vs. input signal
voltage (all types).
219
CD4066B Types
ElECTRICAL CHARACTERISTICS (cont'd)
LIMITS AT INDICATED
TEMPERATURES (OC)
Values at -55, +25, +125 Apply to
D, F, H Packages
at -40, +25, +85 Apply to
Voo
Characteristic
Test Conditions
U
N
I
T
L -______
>--_ _ _
~PLOTTER
x-Y
H P
MOSELEY
1030.&
S
Fig.
7 -
Channel on·srate resisrance measurement
circuit.
Control (VC)
Control Input
Low Voltage,
VILC Max.
Illsl <10pA
VIS = VSS' VOS = VOO
and
VIS = VOO, VOS = VSS
Control Input
High Voltage,
VIHC
Input Current,
liN Max.
Crosstalk (Con,
trol Input to
Signal Output)
Turn·On
Propagation
Oelay
See Fig. 2
VIS
~ V~O
SS = 18 V
VOO -
VCC
~
VOO - VSS
Vc = 10 V (Sq. Wave)
t r , tf = 20 ns
RL = 10 kr2
VIN=VOO
t r , tf = 20 ns
CL = 50 pF
RL = 1 kr2
VIS = VOO, VSS =
RL= 1 kH tognd,
CL=50pF,
Vc = 10 V(Square
wave centered on 5 V)
t r , tf = 20 ns,
Vos = Y,Vos@ 1 kHz
Fig.
8 -
Typical ron characteristics for
1
of 4
channels.
Maximum
Control Input
Repetition Rate
15
9.5
Input
Capacitance,
CIN
5
7.5 JJ.F
Switch Input
lis (rnA)
VDD
(V)
5
5
10
10
15
15
Vis
(V)
0
5
0
10
0
15
-55°C
0.64
-0.64
1.6
-1.6
4.2
-4.2
-40°C
0.61
-0.61
1.5
-1.5
4
-4
+25
0
C
0.51
-0.51
1.3
-1.3
3.4
-3.4
+85
0
C
0.42
-0.42
1.1
-1.1
2.8
-2.8
+125
0
C
0.36
-0.36
0.9
-0.9
2.4
-2.4
Switch Output.
Vas (V)
Min.
4.6
0.5
9.5
1.5
13.5
Max.
0.4
a:
~
I
a
10'
SWITCHING FREQUENCY (f)-IIH,
Fig.
9 -
Power dissipation per package
lIS.
switching
frequency.
r- - - - -
c
~o.
~1-
- - -
- -,
I
: vC'-,,,
I
"001.',,:
I
I
I
~!::~~~~COEN :~~~~ON
~~gi~I~;~~~M2~~ACITANCE:
I NULLED OUT
VOl __
--_I...:,I=-,-_-IL.._ _ _
CO_4_06_6_B
I OF 4 SWITCHES
_---'Lv.,
r-
I
I
I
'.n·~
IvlS-v.,I
C'I*
I
.
*co
~
*
Fig. 10
-
Capacirance test circuit.
Fig.
6-
Determination of r qn as a test condition for control input
high voltage (V ,HC' specif,cat,on.
220 ____________________________
~
________________________________________
II
CD4088B Types
.IOVJ"\....
I~
•
'f
-20nl
ALL UNuSED TERMINALS
ARE CONNECTEO TO Vss
ALL UNUSED INPUTS ARE CONNECTED TO VSS
ALL UNUSED TERMINALS
ARE CONNECTED TO Vss
Fig.
77 -
,)ff-$witch input or output leakage.
Fig.
72 -
Propagation dalay time lignal input (Vi,)
to signsl output (V
0,)'
Fig.
73 -
Crosstslk~ontrollnput
to signal output.
VO'90~-1
201~
00... -0
n~~l
'NPUOS
Yeo
Yoo
o
~
VSS
NOTE
MEASURE INPUTS
SEQUENTIAllY.
TO BOTH YOO ANa VSS
CONNECT All UNUSEO
INPUTS TO r..THER
YOO OR VSS
MEASURE CONTROL
INPUTS ONLY
+IO~
'r'I,-20ns
Vc
'-----'I\-~
ALL I NUSEO TERMINALS ARE CONNECTED TO VSS
YSS
Fig.
74 -
PrClpagation delay tpLH' tpHL control-
sigllaloutput. Delay
is
measured at
Vos lellel of +7096 from ground (turn-onJ
or ,n-state output lellel (turn-offJ.
ALL UNuSEO INPuTS ARE CONNECTED TO Vss
F;g.
75-
Maximum al/owable control input
repetition rate.
Fig.
76 -
Input leakage current test circuit.
SIGNAL.S
I~PUTS
O~----~~~----------{
O~----~~~-----------~
O~
____
~C~H'~NN~E~L~l
__________
.~
O~----~~·~----------·~
P4C'<4G[
2 - C040018
-\~
10
CHAN I
CHAN 21 CHAN' I CHAN 4,
I - C0404ge
2 -C040188
CLOCK
I l J U L J l ; V O O
,lAX ALLOWABLE
·.IGHAL LEvEL
-
-
-lO"""oo-VsSI
1
,'Iss
------rrfTl
~IOK
Fig.
17-
4-channel PAM multiplex system diagram.
221
CD4066B Types
ANALOG INPUTS
I
(!
5
v)
Fig.
18 -
Bidirectional signal transmission via digital control logic.
(l7~3-1
69-77
955)
C040668H
CHIP PHOTOGRAPH
DimenSions In parentheses are In millimeters and
are def/ved from the baSIC Inch dimenSions as In'
dlcated G"d graduations are In mils (1a- 3 Inch).
The photographs and dimensIOns of each CDSIMDS
chip represent a chip when It IS part of the wafer
When the wafer IS cut Into chips. the cleavage
angles are
57°
Instead of 90° with respect to the
face of the chip Therefore, the Isolated chip IS
actually
7
mils (0.
17
mm) larger In both dimenSions.
SPECIAL CONSIDERATIONS -
CD40668
2.
1.
In applications that employ separate
power sources to drive VOO and the
signal inputs, the VOO current
capability should exceed VOO/RL (RL
effective external load of the four
C040668 bilateral switches). This
provision avoids any permanent cur-
rent flow or clamp action on the VOO
supply when power is applied or
removed from the C040668.
=
In certain applications, the external
load-resistor current may Include
both VOO and signal-line com-
ponents. To avoid drawing VOO cur-
rent when switch current flows into
terminals 1,4,8, or 11, the voltage drop
across the bidirectional switch must
not exceed 0.8 volts (calculated from
RON values shown).
No VOO current will flow through RL
if the switch current flows into ter-
minals 2,3,9, or 10.
222 _____________________________________________________________________
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