Semiconductor
CA3262A, CA3262
Quad-Gated, Inverting Power Drivers
Description
The CA3262 and CA3262A are used to interface low-level
logic to high current loads. Each Power Driver has four
inverting switches consisting of a non-inverting logic input
stage and an inverting low-side driver output stage. All inputs
are 5V TTL/CMOS logic compatible and have a common
Enable input. Each output device has independent current
limiting (I
LIM
) and thermal limiting (T
LIM
) for protection from
over-load conditions. Steering diodes connected from each
output (in pairs) to the Clamp pins may be used in
conjunction with external zener diodes to protect the IC
against over-voltage transients that result from inductive load
switching.
To allow for maximum heat transfer from the chip, all ground
pins on the DIP, PLCC and SOIC packages are directly
connected to the mounting pad of the chip. Integral heat
spreading lead frames directly connect the bond pads and
ground leads to conduct heat from the chip junction to the
PC Board for good heat dissipation.
The CA3262 and CA3262A can drive four incandescent
lamp loads without modulating their brilliance when the
“cold” lamps are energized. Outputs may be parallel
connected to drive high current loads. The maximum output
current of each output is determined by the over-current lim-
iting threshold which is typically 1.2A but may be as low as
0.7A.
August 1997
Features
Independent Over-Current Limiting On Each Output
Independent Over-Temperature Limiting On Each Output
Output Drivers Capable of Switching 700mA Load
Inputs Compatible With TTL or 5V CMOS Logic
Suitable For Resistive, Lamp or Inductive Loads
Power-Frame Package Construction For Good Heat
Dissipation
• Operating Temperature Ranges
- CA3262A . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 125
o
C
- CA3262 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
•
•
•
•
•
•
Applications
•
•
•
•
•
•
Solenoids
Relays
Lamps
Steppers
Small Motors
Displays
System Applications
•
•
•
•
Automotive
Appliances
Industrial Controls
Robotics
Ordering Information
PART NUMBER
CA3262E
CA3262AE
CA3262AQ
CA3262AM
TEMP.
RANGE (
o
C)
-40 to 85
-40 to 125
-40 to 125
-40 to 125
PACKAGE
16 Ld PDIP
16 Ld PDIP
28 Ld PLCC
24 Ld SOIC (W)
PKG.
NO.
E16.3
E16.3
N28.45
M24.3
Pinouts
CA3262, CA3262A (PDIP)
TOP VIEW
OUT B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN A
IN B
ENABLE
GND
GND
V
CC
IN C
IN D
GND 5
GND 6
GND 7
GND 8
GND 9
GND 10
GND 11
12 13 14 15 16 17 18
IN D
OUT C
CLAMP
OUT D
IN C
V
CC
NC
25 GND
24 GND
23 GND
22 GND
21 GND
20 GND
19 GND
INDEX
CA3262A (PLCC)
TOP VIEW
CLAMP
OUT A
ENABLE
CA3262A (SOIC)
TOP VIEW
PRELIMINARY
OUT A
CLAMP
OUT B
NC
GND
GND
GND
GND
NC
1
2
3
4
5
6
7
8
9
24 IN A
23 IN B
22 ENABLE
21 NC
20 GND
19 GND
18 GND
17 GND
16 NC
15 V
CC
14 IN C
13 IN D
IN A
CLAMP
OUT B
GND
GND
OUT C
CLAMP
OUT D
4
3
2
NC
1
28 27 26
IN B
OUT A
OUT C 10
CLAMP 11
OUT D 12
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1997
File Number
1836.6
1
CA3262A, CA3262
Absolute Maximum Ratings
Logic Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Logic Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Output Voltage, V
CEX
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60V
Output Sustaining Voltage, V
CE(SUS)
. . . . . . . . . . . . . . . . . . . . 40V
Output Transient Current . . . . . . . . . . . . . . . . . . . . . . . . . . (Note 1)
Output Load Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (Note 2)
Thermal Information
Thermal Resistance (Typical, Note 3)
θ
JA
(
o
C/W)
For PC Mount Without Added Copper Ground Area
CA3262E (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . .
60
CA3262AE (PDIP) . . . . . . . . . . . . . . . . . . . . . . . .
60
CA3262AQ (PLCC) . . . . . . . . . . . . . . . . . . . . . . .
45
CA3262AM (SOIC) . . . . . . . . . . . . . . . . . . . . . . .
60
For PC Mount With 2 sq. in. of Added Copper Ground Area
CA3262E (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . .
40
CA3262AE (PDIP) . . . . . . . . . . . . . . . . . . . . . . . .
40
CA3262AQ (PLCC) . . . . . . . . . . . . . . . . . . . . . . .
36
CA3262AM (SOIC) . . . . . . . . . . . . . . . . . . . . . . .
36
See Maximum Power Dissipation vs Temperature curves, Figures
6A and 6B.
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 265
o
C
Operating Conditions
Temperature Range
CA3262AE, CA3262AQ, CA3262AM . . . . . . . . . . -40
o
C to 125
o
C
CA3262E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V
CC
= 5.5V, T
A
= -40
o
C to 125
o
C for CA3262A and V
CC
= 5.5V, T
A
= -40
o
C to 85
o
C for CA3262
Unless Otherwise Specified
CA3262
CA3262A
MAX
100
-
MIN
-
40
TYP
0.6
-
MAX
50
-
UNITS
µA
V
PARAMETER
Output Leakage Current
Output Sustaining
Voltage
Collector Emitter
Saturation Voltage
(See Figures 4B and 5B)
SYMBOL
I
CEX
V
CE(SUS)
Note 5
TEST CONDITIONS
V
CE
= 60V, V
ENABLE
= 0.8V
MIN
-
40
TYP
-
-
V
CE(SAT)
V
IN
= 2V, V
CC
= 4.75V
I
C
= 100mA
I
C
= 200mA
I
C
= 300mA
I
C
= 400mA
I
C
= 500mA
I
C
= 600mA
I
C
= 700mA, T
A
= -40
o
C
-
-
-
-
-
-
-
-
2
V
IN
= 0.8V
V
IN
= V
ENABLE
= 5.5V,
I
C
= 600mA
V
IN
= 2V, V
ENABLE
= 5.5V,
I
OUTA
= 250mA, I
OUTB
= 250mA,
I
OUTC
= 250mA, I
OUTD
= 250mA
V
IN
= 0V
I
R
V
F
V
R
= 60V
I
F
= 1A, V
IN
= 0V
I
F
= 1.5A, V
IN
= 0V
t
PHL
, t
PLH
I
OUT
= 500mA
I
LIM
V
OUT
= 2V, V
IN
= 5.5V,
V
ENABLE
= 5.5V
-
-
-
-
0.7
-
-
-
-
-
100
1.7
2.1
8
(Note 1)
-
-
-
-
0.7
-
-
-
-
-
50
1.7
2.1
8
(Note 1)
µA
V
V
µs
A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.25
-
-
0.4
-
0.6
0.6
0.8
-
10
10
70
-
-
-
-
-
-
-
-
2
-
-
-
0.05
-
-
0.2
-
-
-
-
-
0.75
-
(Note 4)
0.15
0.2
0.25
0.3
0.4
0.5
0.5
0.8
-
10
10
55
V
V
V
V
V
V
V
V
V
µA
µA
mA
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Supply Current,
All Outputs ON,
(See Figures 4A and 5A)
Supply Current, All
Outputs OFF,
(See Figures 4A and 5A)
Clamp Diode Leakage
Current
Clamp Diode Forward
Voltage,
(See Figures 4D and 5D)
Turn-On Delay,
(See Figures 4C and 5C)
Over Current Limiting
DESIGN PARAMETERS
Over Temperature Limiting
(Junction Temperature)
V
IL
V
IH
I
IL
I
IH
I
CC(ON)
I
CC(OFF)
-
-
5
-
(Note 4)
5
mA
T
LIM
-
155
-
-
155
-
o
C
3
CA3262A, CA3262
Electrical Specifications
V
CC
= 5.5V, T
A
= -40
o
C to 125
o
C for CA3262A and V
CC
= 5.5V, T
A
= -40
o
C to 85
o
C for CA3262
Unless Otherwise Specified
(Continued)
CA3262
PARAMETER
Input Capacitance, Input
Enable Capacitance
NOTES:
1. The CA3262 and CA3262A have on-chip limiting for transient peak currents. Under short-circuit conditions with voltage applied to the collector
of the output transistor and with the output transistor turned ON, the current will increase to 1.2A, typical. Over-Current Limiting protects a short
circuit condition for a normal operating range of output supply voltage. During a short circuit condition, the output driver will shortly thereafter
(approx. 5ms) go into Over-Temperature Limiting. While Over-Current Limiting may range to peak currents greater than 2A, each output will
typically withstand a direct short circuit up to supply voltage levels of 16V. Excessive dissipation before thermal limiting occurs may cause dam-
age to the chip for supply voltages greater than 18V. The CA3262 and CA3262A are rated to withstand peak current, cold turn-on conditions of
#168 or #194 lamp loads.
2. The total DC current for the CA3262 and CA3262A with all 4 outputs ON should not exceed the total of (4 x 0.7A + Max. I
CC
) ~ 2.85A. This level
of current will significantly increase the chip temperature due to increased dissipation and may cause thermal shutdown in high ambient tem-
perature conditions (See Absolute Maximum Ratings for Dissipation). Any one output may be allowed to exceed 0.7A but may be subject to
Over-Current Limiting above the I
LIM
min. limit of 0.7A. As a practical limit, no single output should be loaded to more than 1A (Max).
3. Normal applications require a surface mount of the 28 lead PLCC and 24 lead SOIC packages on a PC Board. The PLCC, SOIC and PDIP
packages have power lead frame construction through the ground pins to conduct heat from the frame to the PC Board ground area. Thermal
resistance,
θ
JA
, is given for a surface mount of the 28 lead PLCC and the 24 lead SOIC packages on a 1 oz. copper PC board with minimal
ground area and with 2 square inches of ground area.
4. I
CC
varies with temperature. Typically, I
CC(ON)
is 18mA at 125
o
C and 41mA at -40
o
C. Typically, I
CC(OFF)
is 2.2mA at 125
o
C and 1.2mA at
-40
o
C.
5. Tested with a switched-off 500mA Load of 120mH (with 24Ω series resistance), V
BATT
= 12V and the outputs (V
CE
) clamped to +40V maximum
with an external zener diode.
SYMBOL
C
IN
C
EN
TEST CONDITIONS
MIN
-
-
TYP
MAX
-
-
MIN
-
-
CA3262A
TYP
3
4.4
MAX
-
-
UNITS
pF
pF
-
-
Applications
Typical circuit configurations for applying the CA3262 and
CA3262A are shown in the application circuit of Figure 2. To
their rated capabilities, both circuits can be used to drive induc-
tive, resistive and lamp loads. The CA3262A has a lower V
SAT
than the CA3262 and is rated for 125
o
C ambient temperature
applications. The CA3262 data sheet rating is 85
o
C. Otherwise,
the protection features described apply to both the CA3262 and
CA3262A.
The maximum voltage for full load current switching is the
output sustaining voltage, V
CE(SUS)
which should not exceed
40V. To provide a means of over-voltage protection, on-chip
steering diodes are connected from each output to one of two
CLAMP pins. Over-voltage pulses may be generated from
inductive load switching and must be clamped or limited to a
peak voltage less than V
CE(SUS)
. To limit an inductive voltage
pulse, a zener diode should be connected to the appropriate
CLAMP pin. When the voltage pulse exceeds the zener thresh-
old, the excess energy is dumped to ground via the on-chip
steering diode and the external zener diode.
The on-chip diodes may be used in a free-wheeling mode by
connecting the CLAMP pins to an external clamp supply
voltage. Zener diode clamp protection is preferred over the
power supply clamp option, primarily because the power
supplies may be subject to large transient changes; including
turn-ON and turn-OFF conditions where non-tracking conditions
between supplies could allow forward conduction through the
steering diodes. For all transient conditions of either method, the
clamp voltage should greater than the maximum supply voltage
of the switching outputs and less than V
CE(SUS)
.
Note that the rate of change of the output current during load
switching is fast. Therefore, even small values of inductance,
including the inductance of a few meters of hook-up wire to
the load circuit, can generate voltage spikes of considerable
amplitude at the output terminals and may require clamping
to protect the device ratings.
Current-limiting is provided as protection for shorted or over-
loaded output conditions. Voltage is sampled across a small
metal resistor in the emitter of each output stage. When the volt-
age exceeds a preset comparator level, drive is reduced to the
output. Current limiting is sustained unless thermal conditions
exceed the preset thermal shutdown temperature of 155
o
C.
If an output is shorted, the remaining three outputs will
continue to function normally unless the continued heat
spreading is sufficient to raise the junction temperature at any
other output to a level greater than 155
o
C. High ambient tem-
perature conditions may allow this to happen. The degree of
interaction is minimized at chip layout design by separating
the output devices, each to a separate corner of the chip.
As noted, the thermal resistance values of the PDIP, PLCC
and SOIC packages are improved by direct connection of
the leads to the chip mounting pad. For a normal PC Board
application, the thermal resistance coefficient for each pack-
age can be significantly lowered by increasing ground cop-
per area on the PC board next to the ground pins of the IC.
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