CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
T
A
= +25
o
C, V
CC
= 12V, V
S
= 2.85V, V
C
= 2.85V, V
AB
= V
PB
= V
CC
, V
B
adjusted for V
18
= 6.3V, C
X
adjusted
for F
OSC
= 4.43361875MHz, Sandcastle: V
BG
= 8.0V, V
BLANK
= 3.5V - Burst Gate centered on Burst.
These conditions exist except as otherwise noted. See Figure 19 for test circuit
TYPICAL
VALUE
PARAMETER
LUMINANCE SECTION
Input Impedance (Terminal 20)
TEST CONDITIONS
UNITS
6
5
kΩ
pF
V
P-P
MHz
Luminance Channel Input Voltage
Bandwidth of Luminance Channel
Luma Input Signal = 30% Sync.
Luma Input Signal: 0.5V
P-P
(30% Sync) modulated CW
Adj. modulation frequency for -3dB at color outputs.
For Control Characteristics, See Figures 1 and 2.
Luma Input Signal: 0.5V
P-P
(30% Sync)
V
B
0V - 5V,Measured at Pin 18 black level.
See Figures 1 and 2.
0.5
8
Brightness Control Range (Terminal 23)
Output Black Level
Range
Offset
Contrast Control Range (Terminal 22)
0 - 3.5
V
DC
5.9-9.7
0.6 Max.
V
DC
V
DC
V
DC
dB
Luminance Input: 0.5V
P-P
(30% Sync), for Control Characteristics.
See Figure 3
Luminance Input: 0.5V
P-P
(30% Sync), V
C
= 0.5V - 5V measure
Pin 18 black level to maximum white level. See Figure 4.
Luminance Input: 0.5V
P-P
(30% Sync), V
C
= 5V, read black
level to peak white. See Figures 5 and 6.
0-5
Luminance Gain Control Range
32
RGB Output Swing
4
V
P-P
CHROMlNANCE SECTION
Input Impedance (Terminal 4)
See Figures 7 and 8.
4.5
5
Chroma Channel Input Voltage
Chroma
Burst
ACC Range
Input Burst Level for Kill (Note 1)
Adjust chroma input Pin 4 until Pin 2
≤25mV
P-P
.
Measure Burst level at Pin 4.
Chroma Input: Burst = 100mV
P-P
, Chroma = 220mV
P-P
.
Luminance Input: 0.35V
P-P
, V
S
adjusted for Chroma at
Pin 18 = 2V
P-P
. V
C
is adjusted for luminance at Pin 18 = 2V
P-P
,
V
C
is again adjusted for luminance of +6 and -9dB.
Then read chroma percentage difference. See Figure 9.
220
100
+6 - (-20)
10
±5
kΩ
pF
mV
P-P
mV
P-P
dB
mV
P-P
%
Contrast Control Chroma/Luma Tracking
7-57
Specifications CA3194
Electrical Specifications
T
A
= +25
o
C, V
CC
= 12V, V
S
= 2.85V, V
C
= 2.85V, V
AB
= V
PB
= V
CC
, V
B
adjusted for V
18
= 6.3V, C
X
adjusted
for F
OSC
= 4.43361875MHz, Sandcastle: V
BG
= 8.0V, V
BLANK
= 3.5V - Burst Gate centered on Burst.
These conditions exist except as otherwise noted. See Figure 19 for test circuit
(Continued)
TYPICAL
VALUE
0-5
2.5
PARAMETER
Saturation Control Range (Terminal 3)
Maximum Chroma Output Voltage (Terminal 2)
TEST CONDITIONS
For control characteristic, see Figure 10.
Chroma Input: Burst = 100mV
P-P
, Chroma = 220mV
P-P
.
Adjust V
C
and V
S
for maximum Pin 2 output.
UNITS
V
DC
V
P-P
OSCILLATOR SECTION
Pull-In Range
Chroma Input: Burst = 100mV
P-P
, Chroma = 220mV
P-P
.
Adjust C
X
for HI/LO f
OSC
without Chroma signal.
Apply signal to lock.
±500
Hz
Static Phase Error
2
Deg./
100Hz
DEMODULATOR SECTION
R-Y Demodulator Conversion Gain
Chroma Input: Burst =100mV, Chroma = 220mV
P-P
,V
ø
.
Adjust V
C
for V18 = 1V. Read V15. Calculate V18/V15.
Chroma Input: Burst = 100mV
P-P
, U
ø
. Read V16 and V14.
Calculate V16/V14. V
C
remains as for R-Y gain.
Chroma Input: Burst =100mV
P-P
, Chroma = 220mV
P-P
, U
ø
read V17 and V16, Calculate V17/V16. V
C
remains as above.
Chroma Input: Burst =100mV
P-P
, Chroma = 220mV
P-P
, V
ø
.
Read V17 and V18. Calculate V17/V18. V
C
remains as above.
No Chroma or Luma Input. Read residual carrier at outputs.
10
Ratio
B-Y Demodulator Conversion Gain
18
Ratio
G-Y/B-Y Matrix Ratio
0.2
Ratio
G-Y/R-Y Matrix Ratio
0.5
Ratio
Sub-Carrier and Harmonic Content at Outputs
SANDCASTLE PULSE
Horizontal and Vertical Blanking Pedestal
Burst Gate Pulse
NOTES:
30
mV
P-P
2-5
6.5 - V
CC
V
V
1. If a different value is desired, see the Threshold Adjustment Circuit of Figure 17.
2. Use of the circuit of Figure 18 is suggested to prevent increased color saturation at low level RF signals.
3. The reference voltage can be adjusted by changing the values of the voltage divider.
Circuit Description
(See Block Diagram and Figure 20)
The chroma signal is externally separated from the video
signal by means of a bandpass or high-pass filter and
applied to pin 4. The burst is separated in the first chroma
stage and applied to the synchronous detector which pro-
vides information to sample-and-hold circuits for APC
(phase-locked loop), ACC (automatic chroma gain control)
and identification and killing. The 4.43MHz crystal oscillator
is phase-locked to the burst and provides 0 degrees and 90
degrees (via an external phase shifter) carriers to the
chroma demodulators. The burst and chroma amplitude at
the output of the first chroma amplifier is kept constant by
the automatic gain control.
The second chroma stage provides saturation control (pin 3)
which tracks the contrast control in the luminance channel.
This stage is also used for color killing.
A buffer stage drives the external PAL delay line. The sepa-
rated U and V signals are applied to pins 14 and 15, respec-
tively, and demodulated. A standard G-Y matrix is included
on the chip.
The luminance signal passes through the subcarrier trap
and through the luminance delay line and enters the chip at
pin 20. Contrast and brightness control is provided before
the luminance signal is combined with the color difference
signals in the Y matrix. Average and peak beam limiting cir-
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