from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Static Electrical Specifications
At T
A
= -40 to +85
o
C, V
DD
±5%,
Unless Otherwise Specified
CONDITIONS
CDP1877
LIMITS
CDP1877C
MAX
50
200
-
-
-
-
0.1
0.1
-
-
1.5
3
-
-
±1
±2
±1
±10
1.0
3.0
7.5
15
MIN
-
-
1.6
-
-1.15
-
-
-
4.9
-
-
-
3.5
-
-
-
-
-
-
-
-
-
(NOTE1)
TYP
0.02
-
3.2
-
-2.3
-
0
-
5
-
-
-
-
-
-
-
±10
-4
-
0.5
-
5
10
MAX
200
-
-
-
-
-
0.1
-
-
-
1.5
-
-
-
±1
-
±1
-
1.0
-
7.5
15
UNITS
µA
µA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
µA
µA
µA
µA
mA
mA
pF
pF
PARAMETER
Quiescent Device
Current
Output Low Drive (Sink)
Current
Output High Drive
(Source) Current
Output Voltage Low Level
(Note 2)
Output Voltage High Level
(Note 2)
Input Low Voltage
I
DD
V
O
(V)
-
-
I
OL
0.4
0.5
I
OH
4.6
9.5
V
OL
-
-
V
OH
-
-
V
IL
0.5, 4.5
0.5, 9.5
V
IN
(V)
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
-
-
-
0, 5
0, 10
0, 5
0, 10
-
-
-
-
V
DD
(V)
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
-
-
MIN
-
-
1.6
2.6
-1.15
-2.6
-
-
4.9
9.9
-
-
3.5
7
-
-
-
-
-
-
-
-
(NOTE1)
TYP
0.01
1
3.2
5.2
-2.3
-5.2
0
0
5
10
-
-
-
-
-
-
±10
-4
±10
-4
0.5
1.9
5
10
Input High Voltage
V
IH
0.5, 4.5
0.5, 9.5
Input Leakage Current
I
IN
Any
Input
0, 5
0, 10
Three-State Output
Leakage Current
Operating Device Current
(Note 3)
Input Capacitance
Output Capacitance
NOTES:
I
OUT
I
OPER
-
-
C
IN
C
OUT
-
-
1. Typical values are for T
A
= +25
o
C and nominal V
DD
.
2. I
OL
= I
OH
= 1µA
3. Operating current is measured under worst-case conditions in a 3.2MHz CDP1802A system, one PIC access per instruction cycle.
4-83
CDP1877, CDP1877C
Operating Conditions
At T
A
= Full package temperature range. For maximum reliability, operating conditions should be selected so
that operation is always within the following ranges:
LIMITS
CDP1877
PARAMETER
DC Operating Voltage Range
Input Voltage Range
MIN
4
V
SS
MAX
10.5
V
DD
MIN
4
V
SS
CDP1877C
MAX
6.5
V
DD
UNITS
V
V
TPA
CS
CS
CA/A
X
CA/A
Y
4-BIT
LATCH
TPB
MWR
MRD
DECODER
CS
WRITE PAGE REGISTER
WRITE CONTROL REGISTER
WRITE MASK REGISTER
READ STATUS REGISTER
READ POLLING REGISTER
READ LONG BRANCH
CASC
READ
STATUS
REGISTER
WRITE
MASK
REGISTER
INT
WRITE
PAGE
REGISTER
READ
LONG
BRANCH
EN
CLEAR
EN
HIGH
VECTOR
ADDRESS
EN
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
INTERRUPT
LATCH/
STATUS
REGISTER
MASK
REGISTER
PRIORITY
ENCODER/
VECTOR
ADDRESS
GENERATION
LONG
BRANCH
INSTRUCTION
GENERATE
LOGIC
READ POLLING
REGISTER
EN
LOW
VECTOR
ADDRESS
CLEAR
CLEAR
INTERVAL
UPPER BITS
MWR
MRD
BUS 0
BUS 1
DATA
BUS
BUFFERS
BUS 2
BUS 3
BUS 4
CONTROL REGISTER
WRITE
CONTROL
REGISTER
BUS 5
BUS 6
BUS 7
FIGURE 1. FUNCTIONAL DIAGRAM FOR CDP1877
4-84
CDP1877, CDP1877C
Functional Definitions for CDP1877 and CDP1877C Terminals
TERMINAL
V
DD
- V
SS
BUS0 - BUS7
IR0 - IR7
INTERRUPT
MRD, MWR
TPA, TPB
CS, CS
CS/A
X
, CS/A
Y
CASCADE
Power
Data Bus - Communicates Information to and from CPU
Interrupt Request Lines
Interrupt to CPU
Read/Write Controls from CPU
Timing Pulses from CPU
Chip Selects, Enable Chip if Valid during TPA
Used as a Chip Select during TPA and as a Register Address During Read/Write Operations
Used for Cascading Several PIC Units. The INTERRUPT Output from a Higher
Priority PIC can be Tied to this Input, or the Input can be Tied to V
DD
if Cascading is Not Used.
Bidirectional
Input
Output
Input
Input
Input
Input
Input
USAGE
TYPE
PIC Programming Model
INTERNAL REGISTERS
The PIC has three write-only programmable registers and
two read-only registers.
Page Register
This write only register contains the high order vector
address the device will issue in response to an interrupt
request. This high-order address will be the same for any of
the 8 possible interrupt requests; thus, interrupt vectoring dif-
fers only in location within a specified page.
BUS 0
A14
A13
PAGE REGISTER BITS
A12
A11
A10
A9
A8
WRITE ONLY
BUS 7
A15
Control Register
The upper nibble of this write-only register contains the low
order vector address the device will issue in response to an
BUS 7
CONTROL REGISTER BITS
B7
B6
B5
B4
B3
B2
B1
B0
interrupt request. The lower nibble is used for a master
interrupt reset, master mask reset and for interval select.
BUS 0
WRITE ONLY
INTERVAL SELECT DETERMINES
NUMBER OF BYTES ALLOCATED TO
EACH INTERRUPT SERVICE ROUTINE
BIT 1
0
0
BIT 0
0
1
INTERVAL
2
4
1
0
8
1
1
16
MASTER MASK RESET
0 RESETS ALL MASK REGISTER BITS
1 NO CHANGE
MASTER INTERRUPT RESET
0 RESETS ALL INTERRUPT LATCHES, CLEARS ANY
PENDING INTERRUPTS
1 NO CHANGE
SETS UPPER BITS OF THE LOW ORDER VECTOR ADDRESS AS A
FUNCTION OF THE INTERVAL SELECT
4-85
CDP1877, CDP1877C
The Low Order Vector Address will be set according to the table below:
LOW ADDRESS BITS
INTERVAL SELECTED NO. OF BYTES
2
4
8
16
NOTES:
1. X = Don’t Care
2. All Don’t Care addresses and addresses A0-A3 are determined by interrupt request.
BIT B7
SETS A7
SETS A7
SETS A7
SETS A7
BIT B6
SETS A6
SETS A6
SETS A6
X
BIT B5
SETS A5
SETS A5
X
X
BIT B4
SET A4
X
X
X
Mask Register
A ”1” written into any location in this write only register will
mask the corresponding interrupt request line. All interrupt
inputs (except CASCADE) are maskable.
BUS 7
M7
M6
M5
MASK REGISTER BITS
M4
M3
M2
M1
BUS 0
M0
WRITE ONLY
Status Register
In this read only register a “1” will be present in the
corresponding bit location for every masked or unmasked
pending interrupt.
BUS 7
S7
S6
S5
STATUS REGISTER BITS
S4
S3
S2
S1
BUS 0
S0
READ ONLY
Polling Register
This read only register provides the low order vector address
and is used to identify the source of interrupt if a polling
technique, rather than interrupt servicing, is used.
BUS 7
P7
P6
P5
POLLING REGISTER BITS
P4
P3
P2
P1
BUS 0
P0
READ ONLY
RESPONSE TO INTERRUPT (AFTER S3 CYCLE)
The PIC’s response to interrogation by the CPU is always 3
bytes long, placed on the data bus in consecutive bytes in
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