CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
At T
A
= Full Package Temperature Range. For Maximum Reliability, Operating Conditions Should be
Selected so that Operation is Always within the Following Ranges:
LIMITS
CDP1852
CDP1852C
MAX
10.5
V
DD
MIN
4
V
SS
MAX
6.5
V
DD
UNITS
V
V
PARAMETER
DC Operating Voltage Range
Input Voltage Range
MIN
4
V
SS
Functional Diagram
CSI/CSI
(NOTE 1)
CS2
MODE
CLOCK
CLEAR
1
DEVICE
SELECT
DECODE
CONTROL
LOGIC
23
SR/SR
(NOTE 1)
13
2
11
14
24
12
V
DD
V
SS
MODE 0
P1
P23
CSI
SR
MODE 1
CSI
SR
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
3
5
7
9
16
18
20
22
RESET
CLOCK
ENABLE
THREE-
STATE
OUTPUT
DRIVERS
8-BIT
DATA
REGISTER
4
6
8
10
15
17
19
21
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
NOTE:
1. Polarity depends on mode.
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM FOR CDP1852
A CLEAR control is provided for resetting the port’s register
(DO0-DO7 = 0) and service request flip-flop (input mode:
SR/ SR = 1 and output mode: SR/SR = 0).
The CDP1852 is functionally identical to the CDP1852C.
The CDP1852 has a recommended operating voltage range
of 4 to 10.5 volts, and the CDP1852C has a recommended
operating voltage range of 4 to 6.5 volts.
The CDP1852 and CDP1852C are supplied in 24-lead,
hermetic, dual-in-line ceramic packages (D suffix), in 24-lead
dual-in-line plastic packages (E suffix). The CDP1852C is
also available in chip form (H suffix).
2
CDP1852, CDP1852C
Logic Diagram
CS2 13
SR/SR
CS1/CS1
1
23
S
MODE
2
V
SS
R
CL
CLEAR 14
SERVICE
REQUEST
LATCH
D
Q
CLOCK 11
V
DD
p
DI0
3
p
TG
n
p
TG
n
DO0
4
n
V
SS
DO1
DI1
5
6
DO7
DI7 22
21
FIGURE 3. CDP1852 LOGIC DIAGRAM
Static Electrical Specifications
At T
A
= -40
o
C to +85
o
C, Unless Otherwise Specified
CONDITIONS
CDP1852
V
O
(V)
V
IN
(V)
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
V
DD
(V)
5
10
5
10
5
10
5
10
(NOTE1)
TYP
-
-
3.2
6
-2.3
-6
0
0
LIMITS
CDP1852C
(NOTE1)
TYP
-
-
3.2
-
-2.3
-
0
-
PARAMETER
Quiescent Device Current
I
DD
MIN
-
-
1.6
3
-1.15
-3
-
-
MAX
10
100
-
-
-
-
0.1
0.1
MIN
-
-
1.6
-
-1.15
-
-
-
MAX
50
-
-
-
-
-
0.1
-
UNITS
µA
µA
mA
mA
mA
mA
V
V
-
-
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage Low-Level
(Note 2)
I
OL
0.4
0.5
I
OH
4.6
9.5
V
OL
-
-
3
CDP1852, CDP1852C
Static Electrical Specifications
At T
A
= -40
o
C to +85
o
C, Unless Otherwise Specified
(Continued)
CONDITIONS
CDP1852
V
O
(V)
V
OH
-
-
Input Low Voltage
V
IL
0.5,
4.5
0.5,
9.5
Input High Voltage
V
lH
0.5,
4.5
0.5,
9.5
Input Leakage Current
I
lN
-
-
Three-State Output Leakage
Current
Operating Current (Note 3)
I
OUT
0, 5
0, 10
I
DD1
-
-
Input Capacitance
Output Capacitance
NOTES:
1. Typical values are for T
A
= 25
o
C and nominal V
DD
.
2. I
OL
= I
OH
= 1µA
3. Operating current is measured at 2MHz in an CDP1802 system with open outputs and a program of 6N55, 6NAA, 6N55, 6NAA,....
At T
A
= -40
o
C to +85
o
C, V
DD
=
±5%,
t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, C
L
= 100pF,
and 1 TTL Load
LIMITS
V
DD
(V)
(NOTE 1)
TYP
C
IN
C
OUT
-
-
V
IN
(V)
0, 5
0, 10
-
V
DD
(V)
5
10
5
(NOTE1)
TYP
5
10
-
LIMITS
CDP1852C
(NOTE1)
TYP
5
-
-
PARAMETER
Output Voltage High Level
(Note 2)
MIN
4.9
9.9
-
MAX
-
-
1.5
MIN
4.9
-
-
MAX
-
-
1.5
UNITS
V
V
V
-
10
-
-
3
-
-
-
V
-
5
3.5
-
-
3.5
-
-
V
-
10
7
-
-
±1
±2
±1
±2
300
800
7.5
7.5
-
-
-
±1
-
±1
-
300
-
7.5
-
V
µA
µA
µA
µA
µA
µA
pF
pF
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
-
5
10
5
10
5
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
130
550
5
5
-
-
-
-
-
-
-
-
-
-
-
-
150
-
5
-
Dynamic Electrical Specifications
PARAMETER
MODE 0 - INPUT PORT
(See Figure 4)
Minimum Select Pulse Width
t
SW
MIN
MAX
UNITS
5
10
-
-
-
-
-
-
180
90
90
45
80
40
360
180
180
90
160
80
ns
ns
ns
ns
ns
ns
Minimum Write Pulse Width
t
WW
5
10
Minimum Clear Pulse Width
t
CLR
5
10
4
CDP1852, CDP1852C
Dynamic Electrical Specifications
At T
A
= -40
o
C to +85
o
C, V
DD
=
±5%,
t
R
, t
F
= 20ns, V
IH
= 0.7 V
DD
, V
IL
= 0.3 V
DD
, C
L
= 100pF,
and 1 TTL Load
(Continued)
LIMITS
V
DD
(V)
t
DS
5
10
Minimum Data Hold Time
t
DH
5
10
Data Out Hold Time (Note 2)
t
DOH
5
10
Propagation Delay Times, t
PLH
, t
PHL
Select to Data Out (Note 2)
t
SDO
5
10
Clear to SR
t
RSR
5
10
Clock to SR
t
CSR
5
10
Select to SR
t
SSR
5
10
NOTES:
1. Typical values are for T
A
= 25
o
C and nominal V
DD
.
2. Minimum value is measured from CS2, maximum value is measured from CS1/CS1.
30
15
-
-
-
-
-
-
185
100
170
85
110
55
120
60
370
200
340
170
220
110
240
120
ns
ns
ns
ns
ns
ns
ns
ns
(NOTE 1)
TYP
-10
-5
75
35
185
100
PARAMETER
Minimum Data Setup Time
MIN
-
-
-
-
30
15
MAX
0
0
150
75
370
200
UNITS
ns
ns
ns
ns
ns
ns
Input Port Mode 0 - Typical Operation
General Operation
When the mode control is tied to V
SS
, the CDP1852
becomes an input port. In this mode, the peripheral device
places data into the CDP1852 with a strobe pulse and the
CDP1852 signals the microprocessor that data is ready to be
transferred on the strobe’s trailing edge via the SR output
line. The CDP1802 then issues an input instruction that
enables the CDP1852 to place the information from the
peripheral device on the data bus to be entered into a mem-
ory location and the accumulator of the microprocessor.
Detailed Operation
(See Figure 5)
The STROBE from the peripheral device places DATA into
the 8-bit register of the CDP1852 when it goes high and
latches the DATA on its trailing edge. The SR output is set
low on the strobe’s trailing edge. This output is connected to
a flag line of the CDP1802 microprocessor and software poll-
ing will determine that the flag line has gone low and periph-
eral data is ready to be transferred. The CDP1802 then
issues an input instruction that places an N
X
line high. With
the MRD line also high, the CDP1852 is selected and its out-
put drivers place the DATA from the peripheral device on the
DATA BUS. When the CDP1802 selected the CDP1852, it
also selected and addressed the memory via one of the 16
internal address registers selected by an internal “X” regis-
ter. The data from the CDP1852 is therefore entered into the
memory [Bus
→
M(R(X))]. The data is also transferred to the
D register (accumulator) in the microprocessor (Bus
→
D).
When the CDP1802’s execute cycle is completed, the
CDP1852 is deselected by the N
X
line returning low and its
data output pins are three-stated. The SR output returns
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