from Case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
At T
A
= Full Package-Temperature Range. For Maximum Reliability, Operating Conditions Should be
Selected so that Operation is Always within the Following Ranges:
LIMITS
CDP1851
CDP1851C
MAX
10.5
V
DD
MIN
4
V
SS
MAX
6.5
V
DD
UNITS
V
V
PARAMETER
DC Operating Voltage Range
Input Voltage Range
MIN
4
V
SS
Functional Diagram
DATA
BUS
DATA
BUS
BUFFER
SECTION
A
A0
A1
A2
A3
A4
A5
A6
A7
READY
STROBE
CLOCK
CS
RA0
RA1
WR/RD
RD/WR
TPB
CLEAR
ADDRESS
DECODE
AND
READ/
WRITE
LOGIC
MODE
CONTROL
AND
STATUS
REGISTERS
A INT
B INT
INTERRUPT
MASKING
AND
LOGIC
SECTION
B
B0
B1
B2
B3
B4
B5
B6
B7
READY
STROBE
FIGURE 1. FUNCTIONAL DIAGRAM FOR CDP1851 AND CDP1851C
2
CDP1851, CDP1851C
Static Electrical Specifications
At T
A
= -40
o
C to +85
o
C, V
DD
±5%, Unless Otherwise Specified
CONDITIONS
CDP1851
PARAMETER
Quiescent Device Current
I
DD
V
O
(V)
-
-
Output Low Drive
(Sink) Current
Output High Drive
(Source) Current
Output Voltage Low-Level
(Note 2)
Output Voltage High Level
(Note 2)
Input Low Voltage
I
OL
0.4
0.5
I
OH
4.6
9.5
V
OL
-
-
V
OH
-
-
V
IL
0.5,
4.5
0.5,
9.5
Input High Voltage
V
lH
0.5,
4.5
0.5,
9.5
Input Leakage Current
I
lN
Any
Input
0, 5
0, 10
I
DD1
-
-
Input Capacitance
Output Capacitance
NOTES:
1. Typical values are for T
A
= 25
o
C and nominal V
DD
.
2. I
OL
= I
OH
= 1µA
3. Operating current is measured at 200kHz for V
DD
= 5V and 400kHz for V
DD
= 10V, with open output (worst-case frequencies for
CDP1802A system operating at maximum speed of 3.2MHz).
C
IN
C
OUT
-
-
V
IN
(V)
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
-
-
-
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
-
V
DD
(V)
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
5
10
-
-
MIN
-
-
1.6
2.6
-1.15
-2.6
-
-
4.9
9.9
-
-
3.5
7
-
-
-
-
-
-
-
-
(NOTE1)
TYP
0.01
1
3.2
5.2
-2.3
-5.2
0
0
5
10
-
-
-
-
-
-
-
-
1.5
6
5
10
MAX
50
200
-
-
-
-
0.1
0.1
-
-
1.5
3
-
-
±1
±2
±1
±1
3
12
7.5
15
MIN
-
-
1.6
-
-1.15
-
-
-
4.9
-
-
-
3.5
-
-
-
-
-
-
-
-
-
LIMITS
CDP1851C
(NOTE1)
TYP
0.02
-
3.2
-
-2.3
-
0
-
5
-
-
-
-
-
-
-
-
-
1.5
-
5
10
MAX
200
-
-
-
-
-
0.1
-
-
-
1.5
-
-
-
±1
-
±1
-
3
-
7.5
15
UNITS
µA
µA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
µA
µA
µA
µA
mA
mA
pF
pF
Three-State Output Leakage
Current
Operating Current (Note 3)
I
OUT
Functional Description
The CDP1851 has four modes of operation: input, output,
bidirectional, and bit-programmable. Port A is programmable
in all modes; port B is programmable in all but the
bidirectional mode. A control byte must be loaded into the
control register to program the ports. In the input and output
modes, each port has two handshaking signals, STROBE
and RDY. In the bidirectional mode, port A has four
handshaking signals: A RDY and A STROBE for input, B
RDY and B STROBE for output. If port A is programmed in
the bidirectional mode, port B must be programmed in the
bit-programmable mode. Each terminal of port A or B may
be individually programmed for input or output in the bit-
programmable mode. Since handshaking is not used in this
mode, the RDY and STROBE lines may also be used for bit-
programming if port A is not in the bidirectional mode.
Input Mode
When a peripheral device has data to input, it sends a
STROBE pulse to the PlO. The leading edge of this pulse
clears the RDY line, inhibiting further transmission from the
peripheral. The trailing edge of the STROBE pulse latches the
data into the PlO buffer register and also activates the INT line
to signal the CPU to read this data. The lNT pin can be wired
3
CDP1851, CDP1851C
to the INT pin of the CPU or the EF lines for polling. The CPU
then executes an input or a load instruction, depending on the
mapping technique used. In either case the proper code must
be asserted on the RAO, RA1, and CS lines to read the buffer
register (see Table 6).
The INT line is deactivated on the leading edge of TPB. The
trailing edge of TPB sets the RDY line to signal the periph-
eral that the port is ready to be loaded with new data. If RDY
is low when the input mode is entered (i.e. after a reset), a
“dummy” read must be done to set RDY high and signal the
peripheral device that the port is ready to be loaded.
Output Mode
A peripheral STROBE pulse sent to the PlO generates an
interrupt to signal the CPU that the peripheral device is
ready for data. The CPU executes the proper output or store
instruction. Data are then read from memory and placed on
the bus. The data are latched into the port buffer at the end
of the window when RE/WE = 0 and WR/RE = 1. The RDY
line is also set at this time, indicating to the peripheral that
there is data in the port buffer. The INT line is deactivated at
the beginning of the window. After the peripheral reads valid
port data, it can send another STROBE pulse, clearing the
RDY line and activating the INT line as in the input mode.
Bidirectional Mode
This mode programs port A to function as both an input and
output port. The bidirectional feature allows the peripheral to
TPB
MRD
MWR
TPA
A0
A1
A2
CDP1800
A3
FAMILY
A4
µP
A5
A6
A7
V
DD
10kΩ
INT
BUS 0-7
B INT
A INT
BUS 0-7
TPB
WR/RE
RD/WE
CLOCK
RA0
RA1
PIO
NO. 1
CDP1851
A RDY
B RDY
A STROBE
B STROBE
PORT A0 - A7
PORT B0 - B7
control port direction by using both sets of handshake signals.
The port A handshaking pins are used to control input data
from peripheral to PlO, while the port B handshaking pins are
used to control output data from PlO to peripheral. Data are
transferred in the same manner as the input and output
modes. Since A INT is used for both input and output, the sta-
tus register must be read to determine what condition caused
A INT to be activated (see Table 5).
Bit-Programmable Mode
This mode allows individual bits of port A or port B to be
programmed as inputs or outputs. To output data to bits
programmed as outputs, the CPU loads a data byte into the
8-bit port as in the output mode (no handshaking). Only bits
programmed for outputs latch this data. Data must be stable
when reading from bits programmed as inputs, since the
input bits do not latch. When the CDP1851 inputs data to the
CPU the CPU also reads the output bits latched during the
last output cycle. The RDY and STROBE lines may be used
for I/O by using the STROBE/RDY I/O control byte in Table
2. An additional feature available in the bit-programmable
mode is the ability to generate interrupts based on
input/output byte combinations. These interrupts can be
programmed to occur on logic conditions (AND, OR, NAND,
and NOR) generated by the eight I/O lines of each port (The
STROBE and RDY lines cannot generate interrupts).
CS
ADDRESS REGISTER
ADDRESS
8001
8002
8003
8004
8008
800C
SELECTS
No. 1 Control/Status Reg
No. 1 Port A
No. 1 Port B
No. 2 Control/Status Reg
No. 2 Port A
No. 2 Port B
TPB
WR/RE
RD/WE
CLOCK
RA0
RA1
CS
A INT
B INT PIO
NO. 2
CDP1851
A RDY
B RDY
A STROBE
B STROBE
PORT A0 - A7
PORT B0 - B7
FIGURE 2. MEMORY SPACE I/O. THIS CONFIGURATION ALLOWS UP TO FOUR CDP1851s TO OCCUPY MEMORY SPACE 8XXX WITH
NO ADDITIONAL HARDWARE (A4-A5 AND A6-A7 ARE USED AS RA0 AND RA1 ON THE THIRD AND FOURTH PIO’s)
4
CDP1851, CDP1851C
Programming
Initialization and Controls
The CDP1851 PlO must be cleared by a low on the CLEAR
input during power-on to set it for programming. Once
programmed, modes can be changed without clearing
except when exiting the bit-programmable mode. A low on
the CLEAR input sets both ports to the input modes,
disables interrupts, unmasks all bit-programmed interrupt
bits, and resets the status register, A RDY, and B RDY.
Mode Setting
The control register must be sequentially loaded with the
appropriate mode set control bytes in order as shown in Table
1 (i.e. input mode then output mode, etc.). Port A is set with
the SET A bit = 1 and port B is set with the SET B bit = 1. If a
port is set to the bit-programmable mode, the bit-programming
control byte from Table 2 must be loaded. A bit is programmed
for output with the I/O bit = 1 and for input with the I/O bit = 0.
The STROBE and RDY lines may be programmed for input or
output with the STROBE/RDY control byte of Table 2. Input
data on the STROBE and RDY lines is detected by reading
the status register. When using the STROBE or RDY lines for
output, the control byte must be loaded every time output data
is to be changed. To program logical conditions that will gen-
erate an interrupt, the interrupt control byte of Table 3 must be
loaded. An interrupt mask of the eight I/O lines may be loaded
next, if bit D4 (mask follows) of the interrupt control byte = 1.
The I/O lines are masked if the corresponding bit of the inter-
rupt mask register is 1, otherwise it is monitored. Any combi-
nation of masked bits are permissible, except all bits masked
(mask = FF).
INT Enable Disable
To enable or disable the INT line in all modes, the interrupt
ENABLE/DISABLE byte must be loaded (see Table 4). Inter-
rupts can also be detected by reading the status register
(see Table 5). All interrupts should be disabled when
programming or false interrupts may occur. The INT outputs
are open drain NMOS devices that allow wired O Ring (use
10K pull-up registers).
GENERATE CLEAR PULSE
AT PIN 13
SET PORTS A AND B
TO INPUT, OUTPUT, OR
BIT-PROGRAMMABLE MODE
USING TABLE 1
YES
IS
EITHER PORT
SET TO THE
BIT-PROGRAMMABLE
MODE 3
NO
PERFORM FOLLOWING
SEQUENCE BEFORE
PROGRAMMING PORT A TO
BIDIRECTIONAL MODE
NOW SET PORT A TO
BIDIRECTIONAL MODE,
IF DESIRED
SET BIT DIRECTION
USING TABLE 2
SET MASTER INTERRUPT
ENABLE/DISABLE
USING TABLE 4
WILL
INTERRUPTS
BE USED FOR
BIT-PROGRAMMED
PORT?
NO
MAIN PROGRAM
REPEAT FOR EACH
BIT-PROGRAMMABLE
PORT
YES
REPEAT FOR EACH
BIT-PROGRAMMABLE
PORT
SET BIT LOGICAL
CONDITIONS AND
MASKING USING
TABLE 3
FIGURE 3. A FLOW CHART GUIDE TO CDP1851 MODE PROGRAMMING
NOTES:
1. STROBE/READY I/O Control Byte (Table 2) is also used to output data to STROBE and READY lines when bit-programmed.
2. Status register (Table 2) is used to input data from STROBE and READY lines when bit-programmed.
3. Interrupt status is also read from status register.
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