April 2004
®
AS7C251MPFD32A
AS7C251MPFD36A
2.5V 1M
×
32/36 pipelined burst synchronous SRAM
Features
•
•
•
•
•
•
Organization: 1,048,576 words × 32 or 36 bits
Fast clock speeds to 200 MHz in LVTTL/LVCMOS
Fast clock to data access: 3.1/3.4/3.8 ns
Fast OE access time: 3.1/3.4/3.8 ns
Fully synchronous register-to-register operation
Dual-cycle deselect
- Single-cycle deselect also available (AS7C252MPFS18A,
AS7C251MPFS32A/ AS7C251MPFS36A)
Asynchronous output enable control
Available in 100-pin TQFP and 165-ball BGA packages
Individual byte write and global byte write
Multiple chip enables for easy expansion
•
•
•
•
•
•
2.5V core power supply
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Boundary scan using IEEE 1149.1 JTAG function
NTD™
1
pipelined architecture available
(AS7C252MNTD18A, AS7C251MNTD32A/
AS7C251MNTD36A)
•
•
•
•
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All
trademarks mentioned in this document are the property of their
respective owners.
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[19:0]
20
CLK
CE
CLR
Q0
Burst logic
Q1
2
2
D
Q
CE
Address
register
CLK
D
DQ
d
Q
Byte write
registers
CLK
D
DQ
Q
c
Byte write
registers
CLK
D
DQ
b
Q
Byte write
registers
CLK
D
DQ
a
Q
Byte write
registers
CLK
D
Enable
CE
register
CLK
Q
1M × 32/36
Memory
array
20
18
20
32/36
32/36
GWE
BWE
BW
d
BW
c
BW
b
BW
a
CE0
CE1
CE2
4
OE
Output
registers
CLK
Input
registers
CLK
ZZ
Power
down
D
Enable
Q
delay
register
CLK
32/36
DQ[a:d]
OE
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-200
5
200
3.1
400
120
70
-167
6
167
3.4
350
110
70
-133
7.5
133
3.8
325
100
70
Units
ns
MHz
ns
mA
mA
mA
4/26/04, v.1.0
Alliance Semiconductor
1 of 22
Copyright © Alliance Semiconductor. All rights reserved.
AS7C251MPFD32A
AS7C251MPFD36A
®
Pin and ball assignment
100-pin TQFP - top view
A
A
CE0
CE1
BWd
BWc
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
NC/DQPc
DQc0
DQc1
V
DDQ
V
SSQ
DQc2
DQc3
DQc4
DQc5
V
SSQ
V
DDQ
DQc6
DQc7
NC
V
DD
NC
V
SS
DQd0
DQd1
V
DDQ
V
SSQ
DQd2
DQd3
DQd4
DQd5
V
SSQ
V
DDQ
DQd6
DQd7
NC/DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
TQFP 14 x 20mm
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb7
DQb6
V
DDQ
V
SSQ
DQb5
DQb4
DQb3
DQb2
V
SSQ
V
DDQ
DQb1
DQb0
V
SS
NC
V
DD
ZZ
DQa7
DQa6
V
DDQ
V
SSQ
DQa5
DQa4
DQa3
DQa2
V
SSQ
V
DDQ
DQa1
DQa0
DQPa/NC
Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration.
4/26/04, v.1.0
LBO
A
A
A
A
A1
A0
NC
A
V
SS
V
DD
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Alliance Semiconductor
2 of 22
AS7C251MPFD32A
AS7C251MPFD36A
®
Ball assignment for 165-ball BGA for 1M x 36
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
BWc
BWd
5
6
7
8
9
10
11
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
LBO
A
A
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
NC
A
CE0
CE1
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Vss
Vss
Vss
Vss
NC
TDI
TMS
CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
1
A0
1
BWE
GWE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TDO
TCK
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
A
A
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
4/26/04, v.1.0
Alliance Semiconductor
3 of 22
AS7C251MPFD32A
AS7C251MPFD36A
®
Functional description
The AS7C251MPFD32A/36A is a high-performance CMOS 32-Mbit synchronous Static Random Access Memory (SRAM)
device organized as 1,048,576 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any
given technology.
Fast cycle times of 5/6/7.5 ns with clock access times (t
CD
) of 3.1/3.4/3.8 ns enable 200,167and 133MHz bus frequencies.
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller
address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally
generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In
a read operation, the data accessed by the current address registered in the address registers by the positive edge of CLK are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the
LBO
input.
With
LBO
unconnected or driven high, burst operations use an interleaved count sequence. With
LBO
driven low, the device
uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more
bytes may be written by asserting BWE and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low.
Address is incremented internally to the next burst address if BWn and ADV are sampled low.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP follow.
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C251MPFD32A/36A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP
and 165-ball BGA.
TQFP and BGA capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Test conditions
V
IN
= 0V
V
OUT
= 0V
Min
-
-
Max
5
7
Unit
pF
pF
TQFP and BGA thermal resistance
Description
Thermal resistance
(junction to ambient)
1
Thermal resistance
(junction to top of case)
1
1 This parameter is sampled
Conditions
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer
4–layer
Symbol
θ
JA
θ
JA
θ
JC
Typical
40
22
8
Units
°C/W
°C/W
°C/W
4/26/04,
v.1.0
Alliance Semiconductor
4 of 22
AS7C251MPFD32A
AS7C251MPFD36A
®
Signal descriptions
Pin
CLK
A,A0,A1
DQ[a,b,c,d]
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b,c,d]
OE
LBO
TDO
TDI
TMS
TCK
ZZ
NC
I/O
I
I
I/O
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
-
Properties
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
SYNC
SYNC
SYNC
Test Clock
ASYNC
-
Description
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,
ADSP is blocked. Refer to the “Synchronous truth table” for more information.
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when
ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and BW[a:d]
control write enable.
Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of
BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d] are inactive,
the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
Selects Burst mode. When tied to V
DD
or left floating, device follows interleaved Burst order. When
driven Low, device follows linear Burst order.
This signal is internally pulled High.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA only).
Test Clock. All inputs are sampled on the rising edge of TCK. All outputs are driven from the falling
edge of TCK.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects
Write enable truth table (per byte)
Function
Write All Bytes
Write Byte a
Write Byte c and d
Read
GWE
L
H
H
H
H
H
BWE
X
L
L
L
H
L
BWa
X
L
L
H
X
H
BWb
X
L
H
H
X
H
BWc
X
L
H
L
X
H
BWd
X
L
H
L
X
H
Key:
X = don’t care, L = low, H = high, n = a, b, c, d;
BWE
,
BWn
= internal write signal.
4/26/04, v.1.0
Alliance Semiconductor
5 of 22
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