D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
SN54ABT162825, SN74ABT162825
18 BIT BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCBS474D − JUNE 1994 − REVISED JUNE 2004
D
Members of the Texas Instruments
D
D
D
D
D
D
Widebus
Family
Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
Typical V
OLP
(Output Ground Bounce)
<1 V at V
CC
= 5 V, T
A
= 25°C
High-Impedance State During Power Up
and Power Down
I
off
and Power-Up 3-State Support Hot
Insertion
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
SN54ABT162825 . . . WD PACKAGE
SN74ABT162825 . . . DL PACKAGE
(TOP VIEW)
description/ordering information
The ’ABT162825 devices are 18-bit buffers and
line drivers designed specifically to improve both
the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. These devices
provide true data and can be used as two 9-bit
buffers or one 18-bit buffer.
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all nine affected
outputs are in the high-impedance state.
The outputs, which are designed to source or sink
up to 12 mA, include equivalent 25-Ω series
resistors to reduce overshoot and undershoot.
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
GND
GND
2Y1
2Y2
GND
2Y3
2Y4
2Y5
V
CC
2Y6
2Y7
GND
2Y8
2Y9
2OE1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2A8
2A9
2OE2
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
ORDERING INFORMATION
TA
−40°C to 85°C
−55°C to 125°C
PACKAGE†
Tube
SSOP − DL
CFP − WD
Tape and reel
Tube
ORDERABLE
PART NUMBER
SN74ABT1628251DL
SN74ABT162825DLR
SNJ54ABT162825WD
ABT162825
SNJ54ABT162825WD
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
2004, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
1
SCBS474D − JUNE 1994 − REVISED JUNE 2004
SN54ABT162825, SN74ABT162825
18 BIT BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE shall be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each 9-bit buffer)
INPUTS
OE1
L
L
H
X
OE2
L
L
X
H
A
L
H
X
X
OUTPUT
Y
L
H
Z
Z
logic diagram (positive logic)
1OE1
1OE2
1A1
1
56
55
2
1Y1
To Eight Other Channels
28
29
41
16
2OE1
2OE2
2A1
2Y1
To Eight Other Channels
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ABT162825, SN74ABT162825
18 BIT BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
SCBS474D − JUNE 1994 − REVISED JUNE 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V
O
. . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Current into any output in the low state, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance,
θ
JA
(see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54ABT162825
MIN
VCC
VIH
VIL
VI
IOH
IOL
∆t/∆v
∆t/∆V
CC
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Control inputs
Input transition rise or fall rate
Power-up ramp rate
Operating free-air temperature
Data inputs
200
−55
125
0
4.5
2
0.8
VCC
−3
8
9
10
200
−40
85
0
MAX
5.5
SN74ABT162825
MIN
4.5
2
0.8
VCC
−12
12
9
10
ns/V
µs/V
°C
MAX
5.5
UNIT
V
V
V
V
mA
mA
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCBS474D − JUNE 1994 − REVISED JUNE 2004
SN54ABT162825, SN74ABT162825
18 BIT BUFFERS/DRIVERS
WITH 3 STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5 V,
VCC = 4.5 V
VOL
Vhys
II
IOZPU
IOZPD
IOZH‡
IOZL‡
Ioff
ICEX
IO§
Outputs high
ICC
Outputs low
Outputs
disabled
VCC = 5.5 V, IO = 0,
VI = VCC or GND
VCC = 5.5 V,
One input at
3.4 V,
Other inputs at
VCC or GND
VCC = 4.5 V
II = −18 mA
IOH = −1 mA
IOH = −1 mA
IOH = −3 mA
IOH = −12 mA
IOL = 8 mA
IOL = 12 mA
100
VCC = 0 to 5.5 V, VI = VCC or GND
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE = X
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE = X
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE
≥
2 V
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE
≥
2 V
Outputs high
VCC = 0,
VCC = 5.5 V,
VCC = 5.5 V,
VI or VO
≤
4.5 V
VO = 5.5 V
VO = 2.5 V
−25
−75
±1
±50
±50
10
−10
±100
50
−100
2
32
2
1
0.05
1.5
3.5
8
1.5
1
1.5
−25
50
−100
2
32
2
1
0.05
1.5
pF
pF
mA
−25
±1
±50
±50
10
−10
±1
±50
±50
10
−10
±100
50
−100
2
32
2
mA
TA = 25°C
SN54ABT162825
MIN TYP†
MAX
MIN
MAX
−1.2
2.5
3
2.4
2*
0.4
0.8*
0.8
2.5
3
2.4
−1.2
2.5
3
2.4
2
0.65
0.8
V
mV
µA
µA
µA
µA
µA
µA
µA
mA
V
SN74ABT162825
MIN
MAX
−1.2
UNIT
V
VOH
Outputs enabled
Outputs disabled
Data inputs
∆I
CC¶
Control inputs
Ci
Co
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
