SN54LVTH273, SN74LVTH273
3.3 V ABT OCTAL D TYPE FLIP FLOPS
WITH CLEAR
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
D
Support Mixed-Mode Signal Operation
D
D
D
D
(5-V Input and Output Voltages With
3.3-V V
CC
)
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
Support Unregulated Battery Operation
Down To 2.7 V
Buffered Clock and Direct-Clear Inputs
Individual Data Input to Each Flip-Flop
SN54LVTH273 . . . J PACKAGE
SN74LVTH273 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
D
I
off
Supports Partial-Power-Down-Mode
D
D
D
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH273 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
CLR
V
CC
2D
2Q
3Q
3D
4D
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
8Q
8D
7D
7Q
6Q
6D
TOP-SIDE
MARKING
description/ordering information
These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) V
CC
operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D)
inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the
D-input signal has no effect at the output.
ORDERING INFORMATION
TA
PACKAGE†
Tube
SOIC − DW
SOP − NS
−40°C to 85°C
SSOP − DB
TSSOP − PW
CDIP − J
−55°C to 125°C
LCCC − FK
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tube
Tube
ORDERABLE
PART NUMBER
SN74LVTH273DW
SN74LVTH273DWR
SN74LVTH273NSR
SN74LVTH273DBR
SN74LVTH273PW
SN74LVTH273PWR
SNJ54LVTH273J
SNJ54LVTH273FK
LXH273
SNJ54LVTH273J
SNJ54LVTH273FK
LVTH273
LVTH273
LXH273
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
•
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4Q
GND
CLK
5Q
5D
Copyright
2003, Texas Instruments Incorporated
1
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
SN54LVTH273, SN74LVTH273
3.3 V ABT OCTAL D TYPE FLIP FLOPS
WITH CLEAR
description/ordering information (continued)
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR
L
H
H
H
CLK
X
↑
↑
H or L
D
X
H
L
X
OUTPUT
Q
L
H
L
Q0
logic diagram (positive logic)
1D
3
CLK
11
CLK(I)
1D
C1
R
1
R
2
1Q
5
2Q
6
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
2D
4
3D
7
4D
8
5D
13
6D
14
7D
17
8D
18
CLR
2
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
SN54LVTH273, SN74LVTH273
3.3 V ABT OCTAL D TYPE FLIP FLOPS
WITH CLEAR
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, V
O
(see Note 1) . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Current into any output in the low state, I
O
: SN54LVTH273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I
O
(see Note 2): SN54LVTH273 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH273 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance,
θ
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54LVTH273
MIN
VCC
VIH
VIL
VI
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.7
2
0.8
5.5
−24
48
10
MAX
3.6
SN74LVTH273
MIN
2.7
2
0.8
5.5
−32
64
10
MAX
3.6
UNIT
V
V
V
V
mA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
SN54LVTH273, SN74LVTH273
3.3 V ABT OCTAL D TYPE FLIP FLOPS
WITH CLEAR
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
VCC = 2.7 V,
VCC = 3 V
VCC = 2.7 V
VOL
VCC = 3 V
II = −18 mA
IOH = −100
µA
IOH = −8 mA
IOH = −24 mA
IOH = −32 mA
IOL = 100
µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 48 mA
IOL = 64 mA
VI = 5.5 V
VI = VCC or GND
VI = VCC
VI = 0
VI or VO = 0 to 4.5 V
VI = 0.8 V
VI = 2 V
VI = 0 to 3.6 V
Outputs high
Outputs low
0.19
5
0.2
75
−75
SN54LVTH273
MIN TYP†
MAX
−1.2
VCC−0.2
2.4
2
2
0.2
0.5
0.4
0.5
0.55
0.55
10
±1
1
−5
75
−75
500
−750
0.19
5
0.2
mA
mA
µA
10
±1
1
−5
±100
µA
A
µA
0.2
0.5
0.4
0.5
V
VCC−0.2
2.4
V
SN74LVTH273
MIN TYP†
MAX
−1.2
UNIT
V
VOH
Control inputs
II
Data inputs
Ioff
VCC = 0 or 3.6 V,
VCC = 3.6 V,
VCC = 3.6 V
VCC = 0,
VCC = 3 V
II(hold)
Data inputs
VCC = 3.6 V‡,
ICC
∆I
CC§
Ci
VCC = 3.6 V, IO = 0,
VI = VCC or GND
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
VI = 3 V or 0
4
4
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH273
VCC = 3.3 V
±
0.3 V
MIN
fclock
tw
tsu
th
Clock frequency
Pulse duration
Data high or low before CLK↑
Setup time
CLR high before CLK↑
Hold time, data high or low after CLK↑
3.3
2.3
2.3
0
MAX
150
3.3
2.7
2.7
0
3.3
2.3
2.3
0
VCC = 2.7 V
MIN
MAX
SN74LVTH273
VCC = 3.3 V
±
0.3 V
MIN
MAX
150
3.3
2.7
2.7
0
ns
ns
VCC = 2.7 V
MIN
MAX
MHz
ns
UNIT
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54LVTH273, SN74LVTH273
3.3 V ABT OCTAL D TYPE FLIP FLOPS
WITH CLEAR
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVTH273
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
±
0.3 V
MIN
fmax
tPLH
tPHL
tPHL
150
1.6
CLK
CLR
Any Q
Any Q
1.8
1.5
5
4.9
4.4
5.6
5.2
4.8
MAX
VCC = 2.7 V
MIN
MAX
SN74LVTH273
VCC = 3.3 V
±
0.3 V
MIN
150
1.7
1.9
1.6
3.2
3.2
2.7
4.9
4.8
4.3
5.5
5.1
4.7
ns
ns
TYP†
MAX
VCC = 2.7 V
MIN
MAX
MHz
UNIT
† All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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