SAF7113H
9-bit video input processor
Rev. 03 — 9 May 2005
Product data sheet
1. General description
The 9-bit video input processor is a combination of a two-channel analog preprocessing
circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and
gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder
(PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N and
SECAM), a brightness, contrast and saturation control circuit, a multistandard VBI data
slicer and a 27 MHz VBI data bypass.
The pure 3.3 V CMOS circuit SAF7113H, analog front-end and digital video decoder, is a
highly integrated circuit for desktop video applications. The decoder is based on the
principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and
NTSC signals into ITU-R BT 601 compatible color component values. The SAF7113H
accepts as analog inputs CVBS or S-video (Y/C) from TV or VTR sources. The circuit is
I
2
C-bus controlled.
The integrated high performance multistandard data slicer supports several VBI data
standards:
•
Teletext 625 lines: WST (World Standard Teletext) and CCST (Chinese teletext)
•
Teletext 525 lines: US-WST, NABTS (North-American Broadcast Text System) and
MOJI (Japanese teletext)
•
•
•
•
•
Closed caption: Europe and US (line 21)
Wide Screen Signalling (WSS)
Video Programming Signal (VPS)
Time codes (VITC EBU/SMPTE)
High-speed VBI data bypass for Intercast application.
2. Features
s
Four analog inputs, internal analog source selectors, e.g. 4
×
CVBS or 2
×
Y/C or
(1
×
Y/C and 2
×
CVBS)
s
Two analog preprocessing channels in differential CMOS style for best
S/N-performance
s
Fully programmable static gain or automatic gain control for the selected CVBS or Y/C
channel
s
Switchable white peak control
s
Two built-in analog anti-aliasing filters
s
Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or
Y/C-signals are available on the VPO-port via I
2
C-bus control
s
On-chip clock generator
Philips Semiconductors
SAF7113H
9-bit video input processor
s
Line-locked system clock frequencies
s
Digital PLL for horizontal sync processing and clock generation, horizontal and vertical
sync detection
s
Requires only one crystal (24.576 MHz) for all standards
s
Automatic detection of 50 Hz and 60 Hz field frequency and automatic switching
between PAL and NTSC standards
s
Luminance and chrominance signal processing for PAL BGHI, PAL N,
combination PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM
s
User programmable luminance peaking or aperture correction
s
Cross-color reduction for NTSC by chrominance comb filtering
s
PAL delay line for correcting PAL phase errors
s
Brightness Contrast Saturation (BCS) and hue control on-chip
s
Real-time status information output (RTCO)
s
Two multifunctional real-time output pins controlled by I
2
C-bus
s
Multistandard VBI data slicer decoding World Standard Teletext (WST),
North-American Broadcast Text System (NABTS), closed caption, Wide Screen
Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code
(VITC) variants (EBU/SMPTE), etc.
s
Standard ITU-R BT 656 YUV 4 : 2 : 2 format (8-bit) on VPO output bus
s
Enhanced ITU-R BT 656 output format on VPO output bus containing:
x
Active video
x
Raw CVBS data for Intercast applications (27 MHz data rate)
x
Decoded VBI data
s
Boundary scan test circuit complies with the
“IEEE Std. 1149.b1 - 1994”
(ID-Code = 1 7113 02B)
s
I
2
C-bus controlled (full read-back ability by an external controller and bit rate up to
400 kbit/s)
s
Low power (< 0.5 W), low voltage (3.3 V), small package (QFP44)
s
Power saving mode by chip enable input
s
Detection of copy protected input signals according to the Macrovision standard; can
be used to prevent unauthorized recording of pay-TV or video tape signals.
3. Applications
s
s
s
s
s
s
s
Notebook (low power consumption)
PCMCIA card application
AGP based graphics cards
Image processing
Video phone applications
Intercast and PC teletext applications
Security applications.
9397 750 14231
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 9 May 2005
2 of 75
Philips Semiconductors
SAF7113H
9-bit video input processor
4. Quick reference data
Table 1:
Symbol
V
DDD
V
DDA
T
amb
P
A+D
Quick reference data
Parameter
digital supply voltage
analog supply voltage
ambient temperature
analog plus digital power
dissipation
Conditions
Min
3.0
3.1
−40
-
Typ
3.3
3.3
+25
0.34
Max
3.6
3.5
+85
-
Unit
V
V
°C
W
5. Ordering information
Table 2:
Type
number
SAF7113H
Ordering information
Package
Name
QFP44
Description
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
Version
SOT307-2
9397 750 14231
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 9 May 2005
3 of 75
Philips Semiconductors
SAF7113H
9-bit video input processor
6. Block diagram
MULTI-STANDARD DATA SLICER
4
5
7
9
43
44
1
AD2 AD1
6
CON
ANALOG
PROCESSING
CONTROL
Y
Y/CVBS
LUMINANCE
CIRCUIT
I
2
C-BUS CONTROL
I
2
C-BUS
INTERFACE
23
SDA
24
SCL
ANALOG
PROCESSING
AND
ANALOG-TO-
DIGITAL
CONVERSION
C/CVBS
AI11
AI1D
AI12
AOUT
AI21
AI2D
AI22
AGND
VBI DATA BYPASS
UPSAMPLING FILTER
bypass
UV
Y
OUTPUT
FORMATTER
12 to 15,
19 to 22
VPO7
to
VPO0
CHROMINANCE
CIRCUIT
AND
BRIGHTNESS CONTRAST
SATURATION CONTROL
SAF7113H
V
SSA1
V
SSA2
V
DDA1
V
DDA2
TDI
TCK
TMS
TRST
TDO
2
41
3
42
38
37
39
8
36
Y
TEST
CONTROL BLOCK
FOR
BOUNDARY
SCAN TEST
AND
SCAN TEST
18
29
33
34
16
28
CLOCKS
SYNCHRONIZATION
CIRCUIT
LFCO
CLOCK
GENERATION
CIRCUIT
POWER-ON
CONTROL
10
11
40
31
32
XTAL
XTALI
17
LLC
30
V
SSDA
35
26
27
25
mhb690
V
DDDE1
V
DDDA
V
SSDE1
RTS0 RTS1 RTCO
V
DDA0
V
SSA0
CE
V
DDDI
V
DDDE2
V
SSDI
V
SSDE2
Fig 1. Block diagram of SAF7113H
9397 750 14231
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 9 May 2005
4 of 75
Philips Semiconductors
SAF7113H
9-bit video input processor
7. Pinning information
7.1 Pinning
34 V
DDDE2
33 V
DDDA
32 XTALI
31 XTAL
30 V
SSDA
29 V
DDDI
28 V
SSDI
27 RTS1
26 RTS0
25 RTCO
24 SCL
23 SDA
VPO7 12
VPO6 13
VPO5 14
VPO4 15
V
SSDE1
16
LLC 17
V
DDDE1
18
VPO3 19
VPO2 20
VPO1 21
VPO0 22
001aac232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
AI22
V
SSA1
V
DDA1
AI11
AI1D
AGND
AI12
TRST
AOUT
1
2
3
4
5
6
7
8
9
SAF7113H
V
DDA0
10
V
SSA0
11
Fig 2. Pin configuration for QFP44
7.2 Pin description
Table 3:
Symbol
AI22
V
SSA1
V
DDA1
AI11
AI1D
AGND
AI12
TRST
AOUT
V
DDA0
V
SSA0
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
Type
I
P
P
I
I
P
I
I
O
P
P
Description
analog input 22
ground for analog supply voltage channel 1
positive supply voltage for analog channel 1 (3.3 V)
analog input 11
differential analog input for AI11 and AI12; has to be connected to
ground via a capacitor; see application diagram of
Figure 40
analog signal ground connection
analog input 12
test reset input (active LOW), for boundary scan test; see
Table
note 1, Table note 2
and
Table note 3
analog test output; for testing the analog input channels; 75
Ω
termination possible
positive supply voltage (3.3 V) for internal Clock Generation Circuit
(CGC)
ground for internal clock generation circuit
9397 750 14231
Product data sheet
Rev. 03 — 9 May 2005
35 V
SSDE2
42 V
DDA2
41 V
SSA2
44 AI2D
39 TMS
36 TDO
43 AI21
37 TCK
38 TDI
40 CE
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