Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
FEATURES
•
High speed parallel latches
•
Extra data width for wide address/data paths or buses carrying
parity
DESCRIPTION
The 74ABT841 Bus interface register is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT841 consists of ten D-type latches with 3-State outputs.
The flip-flops appear transparent to the data when Latch Enable
(LE) is High. This allows asynchronous operation, as the output
transition follows the data in transition. On the LE High-to-Low
transition, the data that meets the setup and hold time is latched.
Data appears on the bus when the Output Enable (OE) is Low.
When OE is High the output is in the High-impedance state.
•
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
•
Slim DIP 300 mil package
•
Broadside pinout
•
Output capability: +64mA/–32mA
•
Latch-up protection exceeds 500mA per Jedec Std 17
•
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
•
Power-up 3-State
•
Power-up reset
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled;
V
O
= 0V or V
CC
Outputs disabled; V
CC
= 5.5V
TYPICAL
4.1
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ABT841 N
74ABT841 D
74ABT841 DB
74ABT841 PW
NORTH AMERICA
74ABT841 N
74ABT841 D
74ABT841 DB
74ABT841PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
LE
PIN DESCRIPTION
PIN NUMBER
1
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
13
12
24
SYMBOL
OE
D0-D9
Q0-Q9
LE
GND
V
CC
FUNCTION
Output enable input
(active-Low)
Data inputs
Data outputs
Latch enable input (active
falling edge)
Ground (0V)
Positive supply voltage
D8 10
D9 11
GND 12
SA00247
1995 Sep 06
1
853-1628 15703
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
LOGIC SYMBOL
FUNCTION TABLE
INPUTS
OE
LE
H
H
↓
↓
X
L
Dn
L
H
l
h
X
X
OUTPUTS
Q0 – Q9
L
H
L
H
Z
NC
Transparent
Latched
High impedance
Hold
OPERATING
MODE
2
3
4
5
6
7
8
9
10 11
L
L
L
L
H
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
13
1
LE
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
L
23 22 21 20 19 18 17 16 15 14
H = High voltage level
h = High voltage level one set-up time prior to the High-to-Low LE
transition
L = Low voltage level
l = Low voltage level one set-up time prior to the High-to-Low LE
transition
↓
= High-to-Low LE transition
NC= No change
X = Don’t care
Z = High impedance “off” state
SA00244
LOGIC SYMBOL (IEEE/IEC)
1
13
EN
C1
2
3
4
5
6
7
8
9
10
11
1D
23
22
21
20
19
18
17
16
15
14
SA00245
1995 Sep 06
2
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
LOGIC DIAGRAM
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
D8
10
D9
11
D
D
D
D
D
D
D
D
D
D
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
13
LE
1
OE
23
Q0
22
Q1
21
Q2
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
Q9
SA00246
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Storage temperature range
V
O
< 0
output in Off or High state
output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +7.0
–18
–1.2 to +7.0
–50
–0.5 to +5.5
128
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
Min
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
0
–40
4.5
0
2.0
0.8
–32
64
5
+85
LIMITS
Max
5.5
V
CC
V
V
V
V
mA
mA
ns/V
°C
UNIT
1995 Sep 06
3
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
Min
V
IK
Input clamp voltage
V
CC
= 4.5V; I
IK
= –18mA
V
CC
= 4.5V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
OH
High-level output voltage
V
CC
= 5.0V; I
OH
= –3mA; V
I
= V
IL
or V
IH
V
CC
= 4.5V; I
OH
= –32mA; V
I
= V
IL
or V
IH
V
OL
V
RST
I
I
I
OFF
I
PU/PD
I
IH
+ I
OZH
I
IL
+ I
OZL
I
CEX
I
O
I
CCH
I
CCL
I
CCZ
∆I
CC
Additional supply current per
input pin
2
Quiescent supply current
Low-level output voltage
Power-up output low
voltage
3
Input leakage
current
Control pins
Data pins
V
CC
= 4.5V; I
OL
= 64mA; V
I
= V
IL
or V
IH
V
CC
= 5.5V; I
O
= 1mA; V
I
= GND or V
CC
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 5.5V; V
I
= GND or 5.5V
V
CC
= 0.0V; V
O
or V
I
≤
4.5V
V
CC
= 2.0V; V
O
= 0.5V; V
I
= GND or V
CC
;
V
OE
= V
CC
V
CC
= 5.5V; V
O
= 2.7V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 0.5V; V
I
= V
IL
or V
IH
V
CC
= 5.5V; V
O
= 5.5V; V
I
= GND or V
CC
V
CC
= 5.5V; V
O
= 2.5V
V
CC
= 5.5V; Outputs High, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs Low, V
I
= GND or V
CC
V
CC
= 5.5V; Outputs 3–State;
V
I
= GND or V
CC
One input at 3.4V, other inputs at V
CC
or
GND; V
CC
= 5 5V
5.5V
–50
2.5
3.0
2.0
Typ
–0.9
3.5
4.0
2.6
0.42
0.13
±0.01
±5
±5.0
±5.0
5.0
–5.0
5.0
–100
0.5
25
0.5
0.5
05
0.55
0.55
±1.0
±100
±100
±50
50
–50
50
–180
250
38
250
1.5
15
–50
Max
–1.2
2.5
3.0
2.0
0.55
0.55
±1.0
±100
±100
±50
50
–50
50
–180
250
38
250
1.5
15
T
amb
= –40°C
to +85°C
Min
Max
–1.2
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
mA
µA
mA
µA
mA
A
UNIT
Power-off leakage current
Power-up/down 3–state
output current
4
3-State output High current
3-State output Low current
Output high leakage current
Output current
1
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V
CC
between 0V and 2.1V with a transition time of up to 10msec. For V
CC
= 2.1V to V
CC
= 5V
"
10%, a
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
Output enable time
to High and Low level
Output disable time
from High and Low level
2
1
4
5
4
5
2.1
2.0
2.1
2.8
1.0
2.2
2.7
2.8
T
amb
= +25
o
C
V
CC
= +5.0V
Typ
4.1
4.0
4.1
4.6
3.0
4.1
4.7
4.6
Max
5.5
5.5
5.9
6.2
4.5
5.6
6.2
6.1
T
amb
= -40 to
+85
o
C
V
CC
= +5.0V
±0.5V
Min
2.1
2.0
2.1
2.8
1.0
2.2
2.7
2.8
Max
6.2
6.2
6.5
6.7
5.3
6.3
7.1
6.5
ns
ns
ns
ns
UNIT
1995 Sep 06
4
Philips Semiconductors
Product specification
10-bit bus interface latch (3-State)
74ABT841
AC SETUP REQUIREMENTS
GND = 0V, t
R
= t
F
= 2.5ns, C
L
= 50pF, R
L
= 500Ω
LIMITS
SYMBOL
PARAMETER
WAVEFORM
T
amb
= +25
o
C
V
CC
= +5.0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time, High or Low
Dn to LE
Hold time, High or Low
Dn to LE
LE pulse width
High or Low
3
3
1
2.5
1.5
1.5
1.0
3.3
Typ
1.0
0.0
0.2
–0.8
1.9
T
amb
= -40 to +85
o
C
V
CC
= +5.0V
±0.5V
Min
2.5
1.5
1.5
1.0
3.3
ns
ns
ns
UNIT
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 3.0V
LE
V
M
t
w
(H)
t
PHL
V
M
V
M
OE
V
M
t
PZH
V
M
t
PHZ
V
OH
–0.3V
0V
t
PLH
Qn
V
M
Qn
V
M
V
M
SA00248
SA00066
Waveform 1. Propagation Delay, Latch Enable Input to Output,
and Enable Pulse Width
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
Dn
V
M
t
PLH
V
M
t
PHL
OE
V
M
t
PZL
V
M
t
PLZ
Qn
V
M
V
M
Qn
V
M
V
OL
+0.3V
0V
SA00064
SA00067
Waveform 2. Propagation Delay for Data to Outputs
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
Dn
LE
1995 Sep 06
ÉÉÉÉÉÉÉÉÉ ÉÉÉ
É
ÉÉÉ
É
ÉÉÉÉÉÉÉÉÉ ÉÉÉ
ÉÉÉÉÉÉÉ ÉÉÉ
V
M
V
M
V
M
V
M
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
V
M
V
M
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SA00249
Waveform 3. Data Setup and Hold Times
5
嵌入式系统
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