INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT32
Quad 2-input OR gate
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Quad 2-input OR gate
FEATURES
•
Output capability: standard
•
I
CC
category: SSI
GENERAL DESCRIPTION
74HC/HCT32
The 74HC/HCT32 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT32 provide the 2-input OR function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
6
3.5
16
HCT
9
3.5
28
ns
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
Quad 2-input OR gate
PIN DESCRIPTION
PIN NO.
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
SYMBOL
data inputs
data inputs
data outputs
ground (0 V)
positive supply voltage
NAME AND FUNCTION
74HC/HCT32
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
Quad 2-input OR gate
FUNCTION TABLE
INPUTS
nA
L
L
H
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
nB
L
H
L
H
74HC/HCT32
OUTPUT
nY
L
H
H
H
Fig.4 Functional diagram.
Fig.5 Logic diagram 74HC (one gate).
Fig.6 Logic diagram 74HCT (one gate).
December 1990
4
Philips Semiconductors
Product specification
Quad 2-input OR gate
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
nA, nB to nY
t
THL
/ t
TLH
output transition time
+25
typ.
22
8
6
19
7
6
max.
90
18
15
75
15
13
−40
to
+85
min.
max.
115
23
20
95
19
16
−40
to
+125
min.
max.
135
27
23
110
22
19
ns
74HC/HCT32
TEST CONDITIONS
UNIT V
CC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
WAVEFORMS
Fig.7
ns
Fig.7
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: SSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine
∆I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
nA, nB
UNIT LOAD COEFFICIENT
1.20
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HCT
SYMBOL
PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
nA, nB to nY
t
THL
/ t
TLH
output transition time
+25
typ.
11
7
max.
24
15
−40
to
+85
min.
max.
30
19
−40
to
+125
min.
max.
36
22
ns
ns
4.5
4.5
Fig.7
Fig.7
UNIT
TEST CONDITIONS
V
CC
WAVEFORMS
(V)
December 1990
5
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