HM6288 Series
16384-word
×
4-bit High Speed CMOS Static RAM
Description
The Hitachi HM6288 is a high speed 64k static RAM organized as 16-kword
×
4-bit. It realizes high speed
access time (25/35 ns) and low power consumption, using CMOS process technology. It is most
advantageous for the field where high speed and high density memory is required, such as cache memory for
mainframes or 32-bit MPUs. The HM6288, packaged in a 300-mil plastic DIP and SOJ, is available for high
density mounting. A low power version retains data with battery backup.
Features
•
Single 5 V supply arid high density plastic package
•
High speed: fast access time 25/35 ns (max)
•
Low power dissipation:
Active mode 300 mW (typ)
Standby mode 100
µW
(typ)
•
Completely static memory
No clock or timing strobe required
•
Equal access and cycle times.
•
Directly TTL compatible all inputs and outputs
HM6288 Series
Ordering lnformation
Type No.
HM6288P-25
HM6288P-35
HM6288LP-25
HM6288LP-35
HM6288JP25
HM6288JP-35
HM6288LJP-25
HM6288LJP-35
Access Time
25 ns
35 ns
25 ns
35 ns
25 ns
35 ns
25 ns
35 ns
300-mil, 24-pin SOJ (CP-24D)
Package
300-mil, 22-pin plastic DIP (DP-22NB)
Pin Arrangement
HM6288P Series
A0
A1
A2
A3
A4
A5
A6
A7
A8
CS
V
SS
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V
CC
A13
A12
A11
A10
A9
I/O1
I/O2
I/O3
I/O4
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
CS
NC
V
SS
HM6288JP Series
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A13
A12
A11
A10
A9
NC
I/O1
I/O2
I/O3
I/O4
WE
(Top view)
(Top view)
Pin Description
Pin Name
A0–A13
I/O1–I/O4
CS
WE
V
CC
V
SS
Function
Address
lnput/output
Chip select
Write enable
Power supply
Ground
2
HM6288 Series
Block Diagram
A0
A1
A2
A3
A4
A5
A6
I/O1
I/O2
I/O3
I/O4
Input
data
control
A7
CS
WE
Row
decoder
Memory array
128 rows
512 columns
V
CC
V
SS
Column I/O
Column decoder
A13
Truth Table
CS
H
L
L
WE
×
H
L
Mode
Standby
Read
Write
V
CC
Current
I
SB
, I
SB1
I
CC
I
CC
I/O Pin
High-Z
Dout
Din
Ref. Cycle
—
Read cycle 1, 2
Write cycle 1, 2
Note:
×:
Don’t care.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to V
SS
Power dissipation
Operating temperature
Storage temperature
Temperature under bias
Symbol
V
T
P
T
Topr
Tstg
Tbias
Value
–0.5
*
to +7.0
1.0
0 to +70
–55 to +125
–10 to +85
Unit
V
W
°C
°C
°C
Note: V
T
min.: –2.0 V for pulse width
≤
10 ns
3
HM6288 Series
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input high (logic 1) voltage
Input low (logic 0) voltage
Note:
V
IH
V
IL
Min
4.5
0
2.2
–0.5
*1
Typ
5.0
0
—
—
Max
5.5
0
6.0
0.8
Unit
V
V
V
V
1. V
IL
min.: –2.0 V for pulse width
≤
10 ns
DC Characteristics
(Ta = 0 to +70°C, V
CC
= 5 V
±
10%, V
SS
= 0 V)
Parameter
Input leakage current
Output leakage current
Operating power supply current
Standby V
CC
current
Standby V
CC
current 1
Symbol
|I
LI
|
|I
LO
|
I
CC
I
SB
I
SB1
Min
—
—
—
—
—
Typ
* 1
Max
—
—
60
15
0.02
2.0
2.0
120
30
2.0
Unit
µA
µA
mA
mA
mA
Test conditions
V
CC
= Max, Vin = V
SS
to V
CC
CS
= V
IH
, V
I/O
= V
SS
to V
CC
CS
= V
IL
, I
I/O
= 0 mA, min. cycle
CS
= V
IH
, min. cycle
CS
≥
V
CC
– 0.2V,
0 V
≤
Vin
≤
0.2V or V
CC
– 0.2V
≤
Vin
I
SB1*2
Output low voltage
Output high voltage
V
OL
V
OH
—
—
2.4
0.02
—
—
0.1
0.4
—
mA
V
V
I
OL
= 8 mA
I
OH
= –4.0 mA
Notes: 1. Typical values are at V
CC
= 5.0 V, Ta = +25°C and not guaranteed.
2. L-version
Capacitance
(Ta = 25°C, f = 1.0 MHz)
*1
Parameter
Input capacitance
lnput/output capacitance
Note:
Symbol
Cin
C
I/O
Min
—
—
Max
6
8
Unit
pF
pF
Test Conditions
Vin = 0 V
V
I/O
= 0 V
1. This parameter is sampled and not 100% tested.
4
HM6288 Series
AC Characteristics
Test Conditions
•
•
•
•
Input pulse levels: 0 V to 3.0 V
Input and output timing reference levels: 1.5 V
Input rise and fall time: 5 ns
Output load: See figure
+5V
480
Ω
Dout
255
Ω
Dout
255
Ω
+5V
480
Ω
30 pF
*1
5 pF
*1
Output load (A)
Output load (B)
(for t
HZ,
t
LZ,
t
WZ,
and t
OW
)
Note: 1. Including scope and jig.
Read Cycle
HM6288-25
Parameter
Read cycle time
Address access time
Chip select access time
Output hold from address change
Chip selection to output in low-Z
Chip deselection to output in high-Z
Chip selection to power up time
Chip deselection to power down time
Note:
Symbol
t
RC
t
AA
t
ACS
t
OH
t
LZ*1
t
HZ *1
t
PU
t
PD
Min
25
—
—
3
5
0
0
—
Max
—
25
25
—
—
12
—
25
HM6288-35
Min
35
—
—
5
5
0
0
—
Max
—
35
35
—
—
20
—
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
1. Transition is measured
±200
mV from steady state voltage with load (B).
These parameters are sampled and not 100% tested.
5
FPGA/CPLD
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