IDTQS74FCT2244T/AT/CT
HIGH-SPEED CMOS 8-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
HIGH-SPEED CMOS
8-BIT BUFFER/LINE
DRIVER
FEATURES:
•
•
•
•
•
•
IDTQS74FCT2244T/AT/CT
DESCRIPTION:
CMOS power levels: <7.5mW static
Undershoot clamp diodes on all inputs
True TTL input and output compatibility
Ground bounce controlled outputs
Reduced output swing of 0 to 3.5V
Ω
Built-in 25Ω series resistor outputs reduce reflection and other
system noise
• Std., A, and C speed grades with 4.1ns t
PD
for C
• I
OL
= 12mA
• Available in SOIC and QSOP packages
The IDTQS74FCT2244T is an 8-bit buffer/line driver with three-state
outputs and a 25Ω resistor, ideal for driving transmission lines and reducing
system noise. The 2244 series part can replace the 244 series to reduce
noise in an existing design. All inputs have clamp diodes for undershoot
noise suppression. All outputs have ground bounce suppression. Outputs
will not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
1G
1
2G
19
1
A
1
2
18
1
Y
1
2
A
1
11
9
2
Y
1
1
A
2
4
16
1
Y
2
2
A
2
13
7
2
Y
2
1
A
3
6
14
1
Y
3
2
A
3
15
5
2
Y
3
1
A
4
8
12
1
Y
4
2
A
4
17
3
2
Y
4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
DECEMBER 2000
DSC-5398/1
© 2000 Integrated Device Technology, Inc.
IDTQS74FCT2244T/AT/CT
HIGH-SPEED CMOS 8-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1G
1
A
1
2
Y
4
1
A
2
2
Y
3
1
A
3
2
Y
2
1
A
4
2
Y
1
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current Max Current Sink/Pin
Input Diode Current, V
IN
< 0
DC Output Current, V
OUT
< 0
Max
–0.5 to +7
–65 to +150
+120
-20
-50
Unit
V
°C
mA
mA
mA
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
2G
1
Y
1
2
A
4
1
Y
2
2
A
3
1
Y
3
2
A
2
1
Y
4
2
A
1
T
STG
I
OUT
I
IK
I
OK
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4
8
Max.
—
—
Unit
pF
pF
GND
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
1G
-
2G
xA
0
- xA
4
xY
0
- xY
4
Inputs
Outputs
Description
3-State Output Enable Inputs (Active LOW)
FUNCTION TABLE
(1)
Inputs
1
G
2
G
Outputs
xAx
L
H
X
xYx
H
L
Z
L
L
H
L
L
H
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2
IDTQS74FCT2244T/AT/CT
HIGH-SPEED CMOS 8-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%
Symbol
V
IH
V
IL
∆V
T
I
IH
I
IL
I
OZ
I
OR
V
IC
V
OH
V
OL
R
OUT
Parameter
Input HIGH Level
Input LOW Level
Input Hysteresis
Input HIGH Current
Input LOW Current
Off-State Output Current (Hi-Z)
Current Drive
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage
Output Resistance
V
CC
= Max.
V
CC
= Max., V
OUT
= 2V
(2)
V
CC
= Min., I
IN
= –18mA, T
A
= 25°C
(2)
V
CC
= Min.
V
CC
= Min.
V
CC
= Min.
I
OH
= –15mA
I
OL
= 12mA
I
OL
= 12mA
0
≤
V
IN
≤
V
CC
—
50
—
2.4
—
20
—
—
–0.7
—
—
28
±5
—
–1.2
—
0.5
40
µA
mA
V
V
V
Ω
Test Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
TLH
- V
THL
for all inputs
V
CC
= Max.
0
≤
V
IN
≤
V
CC
Min.
2
—
—
—
Typ.
(1)
—
—
0.2
—
Max.
—
0.8
—
±5
Unit
V
V
V
µA
NOTES:
1. Typical values are at V
CC
= 5.0V, +25°C ambient.
2. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
Symbol
I
CC
Parameter
Quiescent Power Supply Current
Test Conditions
(1)
V
CC
= Max.
freq = 0
0V
≤
V
IN
≤
0.2V or
V
CC
- 0.2V
≤
V
IN
≤
V
CC
∆I
CC
Supply Current per Input TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(2)
freq = 0
V
CC
= Max.
Outputs Open and Enabled
One Bit Toggling
50% Duty Cycle
Other inputs at GND or V
CC(3,4)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under DC Electrical Characteristics.
2. Per TTL driven input (V
IN
= 3.4V).
3. For flip-flops, I
CCD
is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of device power consumption
only and does not include power to drive load capacitance or tester capacitance.
4. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
Min.
—
Max.
1.5
Unit
mA
—
2
mA
I
CCD
Supply Current per Input per MHz
—
0.25
mA/
MHz
3
IDTQS74FCT2244T/AT/CT
HIGH-SPEED CMOS 8-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
74FCT2244T
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
(2)
Propagation Delay
xAx to xYx
Output Enable Time
xG
to xYx
Output Disable Time
(3)
xG
to xYx
1.5
7
1.5
5.6
1.5
5.2
ns
74FCT2244AT
Min.
1.5
1.5
Max.
4.8
6.2
74FCT2244CT
Min.
1.5
1.5
Max.
4.1
5.8
Unit
ns
Min.
1.5
1.5
Max.
6.5
8
ns
NOTES:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
2. Minimums guaranteed but not tested.
3. This parameter is guaranteed by design but not tested.
4
IDTQS74FCT2244T/AT/CT
HIGH-SPEED CMOS 8-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
500Ω
Pulse
Generator
V
IN
D.U.T.
50pF
R
T
C
L
500Ω
V
OUT
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Switch
Closed
Open
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
FCTL link
Test Circuits for All Outputs
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
t
REM
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
FCTL link
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
FCTL link
1.5V
1.5V
t
SU
t
H
Pulse Width
Set-Up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
FCTL link
DISABLE
3V
1.5V
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
t
PHZ
0.3V
1.5V
0V
t
PLZ
0V
3.5V
0.3V
V
OL
V
OH
0V
FCTL link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
5
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