HIGH-SPEED 2.5V
16/8K x 8 DUAL-PORT
STATIC RAM
.eatures
x
x
PRELIMINARY
IDT70T06/5L
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 20/25ns (max.)
– Industrial: 25ns (max.)
Low-power operation
– IDT70T06/5L
Active: 200mW (typ.)
Standby: 600µW (typ.)
IDT70T06/5 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
x
x
x
x
x
x
x
x
x
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
LVTTL-compatible, single 2.5V (±100mV) power supply
Available in a 64-pin TQFP and 100-pin
fpBGA
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
.unctional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(2,3)
,
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
A
13R
(1)
A
0R
(2,3)
A
13L
(1)
A
0L
Address
Decoder
14
MEMORY
ARRAY
14
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(3)
INT
L
M/S
SEM
R
INT
R
(3)
5668 drw 01
NOTES:
1. A
13
is a NC for IDT70T05.
2. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
3.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
AUGUST 2002
1
©2002 Integrated Device Technology, Inc.
DSC-5668/1
6.07
IDT70T06/5L
High-Speed 2.5V 16/8K x 8 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Description
The IDT70T06/5 is a high-speed 16/8K x 8 Dual-Port Static RAM. The
IDT70T06/5 is designed to be used as a stand-alone 128K-bit Dual-Port
Static RAM or as a combination MASTER/SLAVE Dual-Port Static RAM
for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-
Port Static RAM approach in 16-bit or wider memory system applications
results in full-speed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 200mW of power.
The IDT70T06/5 is packaged in a 64-pin Thin Quad Flatpack and
100-pin fine pitch Ball Grd Array.
Pin Configurations
(1,2,3,4)
I/O
1L
A
12L
A
11L
A
10L
A
9L
CE
L
A
8L
A
7L
51
A
6L
50
A
5L
49
08/14/02
INDEX
61
60
R/W
L
I/O
0L
OE
L
A
13L
(1)
V
DD
SEM
L
64
62
57
I/O
2L
I/O
3L
I/O
4L
I/O
5L
V
SS
I/O
6L
I/O
7L
V
DD
V
SS
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
55
53
52
63
59
58
56
54
48
47
46
45
44
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
V
SS
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
5668 drw 02
70T06/5PF
PN-64
(5)
64-Pin TQFP
Top View
(6)
43
42
41
40
39
38
37
36
35
,
17
18
19
23
24
20
21
27
I/O
6R
I/O
7R
SEM
R
22
25
A
13R
(1)
V
SS
R/W
R
A
10R
CE
R
A
12R
A
11R
OE
R
A
9R
28
A
8R
A
7R
A
6R
NOTES:
1. A
13
is a NC for IDT70T05.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. PN-64 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
2
A
5R
32
16
34
33
29
30
26
31
IDT70T06/5L
High-Speed 2.5V 16/8K x 8 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3,4)
(con't.)
IDT70T06/5BF
BF100
(5)
100-Pin fpBGA
Top View
(6)
A2
A3
A4
A5
A6
A7
A8
A9
A10
08/14/02
A1
A
6R
B1
A
9R
B2
A
12R
B3
NC
B4
V
SS
B5
V
SS
B6
NC
B7
R/W
R
B8
NC
B9
I/O
7R
B10
NC
C1
NC
C2
A
8R
C3
A
10R
C4
NC
C5
NC
C6
A
13R
(1)
OE
R
C7
C8
NC
C9
I/O
6R
C10
A
3R
D1
A
4R
D2
A
5R
D3
A
7R
D4
NC
D5
NC
D6
CE
R
D7
NC
D8
NC
D9
I/O
3R
D10
A
1R
E1
INT
R
E2
A
2R
E3
NC
E4
A
11R
E5
NC
E6
SEM
R
E7
NC
E8
I/O
5R
I/O
1R
E9
E10
M/S
BUSY
R
F1
F2
A
0R
F3
A
1L
F4
V
SS
F5
V
SS
F6
I/O
4R
F7
I/O
2R
F8
I/O
0R
F9
V
DD
F10
V
SS
G1
BUSY
L
G2
A
0L
G3
NC
G4
V
DD
G5
V
SS
G6
V
DD
G7
I/O
5L
G8
I/O
6L
G9
I/O
7L
G10
INT
L
H1
A
3L
H2
A
6L
H3
NC
H4
NC
H5
SEM
L
H6
NC
H7
I/O
3L
H8
V
SS
H9
I/O
4L
H10
A
2L
J1
A
5L
J2
A
10L
J3
NC
J4
NC
J5
CE
L
J6
J7
NC
NC
J8
NC
J9
I/O
2L
J10
A
4L
K1
A
8L
K2
A
11L
K3
NC
K4
NC
K5
A
13L
(1)
K6
R/W
L
K7
NC
K8
V
SS
K9
I/O
1L
K10
A
7L
A
9L
A
12L
NC
V
DD
V
DD
NC
NC
OE
L
I/O
0L
5668 drw 03
NOTES:
1. A
13
is a NC for IDT70T05.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 1.18 in x 1.18 in x .16 in.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.42
3
IDT70T06/5L
High-Speed 2.5V 16/8K x 8 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
13L
(1)
I/O
0L
- I/O
7L
SEM
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
13R
(1)
I/O
0R
- I/O
7R
SEM
R
INT
R
BUSY
R
M/S
V
DD
V
SS
NOTE:
1. A
13
is a NC for IDT70T05.
Right Port
Chip Enable
Names
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power (2.5V)
Ground (0V)
5668 tbl 01
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
CE
H
L
L
X
R/W
Outputs
OE
X
X
L
H
SEM
H
H
H
X
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
5668 tbl 02
Mode
X
L
H
X
NOTE:
1. A
0L
— A
13L
≠
A
0R
— A
13R
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
CE
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-7
DATA
OUT
DATA
IN
____
Mode
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
5668 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0
- I/O
7
. These eight semaphores are addressed by A
0
- A
2
.
4
IDT70T06/5L
High-Speed 2.5V 16/8K x 8 Dual-Port Static RAM
PRELIMINARY
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM(2)
T
BIAS
T
STG
T
JN
I
OUT
(3)
Rating
Terminal Voltage
with Respect to GND
Temperature Under Bias
Storage Temperature
Junction Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +3.6
-55 to +125
-65 to +150
+150
50
Unit
V
o
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Industrial
Am bient Tem perature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
V
DD
2.5V
+
100mV
2.5V
+
100mV
5668 tbl 05
C
C
C
o
NOTE:
1. This is the parameter T
A
. This is the "instant on" case temperature.
o
mA
5668 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed V
DD
+ 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.4
0
1.7
-0.3
(1)
Typ.
2.5
0
____
____
Max.
2.6
0
V
DD
+0.3
(2)
0.7
Unit
V
V
V
V
5668 tbl 06
Capacitance
(T
A
= +25°C, f = 1.0MHz)
Sym bol
C
IN
C
OUT
Param eter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
5668 tbl 07
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed V
DD
+0.3V.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 2.5V ± 100mV)
70T06/5L
S ym bo l
|I
LI
|
|I
LO
|
V
OL
V
OH
P aram eter
Inp ut Le ak ag e Curre nt
(1)
O utp ut Le ak ag e Curre nt
O utp ut Lo w Vo ltag e
O utp ut Hig h Vo ltag e
T est Co nd iti ons
V
DD
= 2.6V, V
IN
= 0
V
to V
DD
V
O U T
= 0V to V
DD
I
O L
= + 2m A
I
OH
= -2m A
M in .
__ _
__ _
__ _
M ax.
5
5
0.4
__ _
Uni t
µA
µA
V
V
5668 tb l 0 8
2.0
NOTE:
1. At V
DD
< 2.0V input leakages are undefined.
6.42
5
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