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MTB75N06HD
Preferred Device
Power MOSFET
75 Amps, 60 Volts
N−Channel D
2
PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
•
Short Heatsink Tab Manufactured − Not Sheared
•
Specially Designed Leadframe for Maximum Power Dissipation
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (t
p
≤
10 ms)
Drain Current − Continuous
Drain Current
− Continuous @ 100°C
Drain Current
− Single Pulse (t
p
≤
10
µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T
C
= 25°C
(Note 1.)
Operating and Storage Temperature
Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 25 Vdc, V
GS
= 10 Vdc,
I
L
= 75 Apk, L = 0.177 mH, R
G
= 25
Ω)
Thermal Resistance
− Junction to Case
− Junction to Ambient
− Junction to Ambient (Note 1.)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10
seconds
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
Value
60
60
±
20
±
30
75
50
225
125
1.0
2.5
Unit
Vdc
Vdc
1
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
T75N06HD
YWW
2
3
4
D
2
PAK
CASE 418B
STYLE 2
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75 AMPERES
60 VOLTS
R
DS(on)
= 10 mΩ
N−Channel
D
G
S
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
− 55 to 150
E
AS
500
1
Gate
2
Drain
3
Source
R
θJC
R
θJA
R
θJA
T
L
1.0
62.5
50
260
°C/W
T75N06HD = Device Code
Y
= Year
WW
= Work Week
ORDERING INFORMATION
°C
Device
MTB75N06HD
MTB75N06HDT4
Package
D
2
PAK
D
2
PAK
Shipping
50 Units/Rail
800/Tape & Reel
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2000
1
September, 2004 − Rev.xxx
Publication Order Number:
MTB75N06HD/D
MTB75N06HD
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 60 Vdc, V
GS
= 0 Vdc)
(V
DS
= 60 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0 V)
ON CHARACTERISTICS
(Note 2.)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
µAdc)
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 37.5 Adc)
Drain−Source On−Voltage (V
GS
= 10 Vdc)
(I
D
= 75 Adc)
(I
D
= 37.5 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 37.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 3.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 48 Vdc, I
D
= 75 Adc,
V
GS
= 10 Vdc)
(V
DS
= 30 Vdc, I
D
= 75 Adc,
V
GS
= 10 Vdc,
Vdc
R
G
= 9.1
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 75 Adc, V
GS
= 0 Vdc)
(I
S
= 75 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
−
−
t
rr
(I
S
= 75 Adc,
dI
S
/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
2. Pulse Test: Pulse Width
≤
300
µs,
Duty Cycle
≤
2%.
3. Switching characteristics are independent of operating junction temperature.
4. Reflects typical values.
Max limit − Typ
C
pk
=
3 x SIGMA
L
D
−
L
S
−
3.5
7.5
−
−
nH
nH
t
a
t
b
Q
RR
−
−
−
−
0.97
0.88
56
44
12
0.103
1.1
−
−
−
−
−
µC
ns
Vdc
−
−
−
−
−
−
−
−
18
218
67
125
71
16.3
31
29.4
26
306
94
175
100
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
Vd
Vd
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
2800
928
180
3920
1300
252
pF
(C
pk
≥
5.0) (Note 4.)
V
GS(th)
2.0
−
(C
pk
≥
2.0) (Note 4.)
R
DS(on)
−
V
DS(on)
−
−
g
FS
15
0.7
0.53
32
0.9
0.8
−
mhos
8.3
10
Vdc
3.0
8.38
4.0
−
Vdc
mV/°C
mΩ
(C
pk
≥
2.0) (Note 4.)
V
(BR)DSS
60
−
I
DSS
−
−
I
GSS
−
−
−
5.0
10
100
100
nAdc
68
60.4
−
−
Vdc
mV/°C
µAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
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2
MTB75N06HD
TYPICAL ELECTRICAL CHARACTERISTICS
150
125
100
75
50
100°C
25
T
J
= −55°C
0
0
0.5
1
1.5
2
2
3
4
5
6
7
8
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
150
T
J
= 25°C
125
I D , DRAIN CURRENT (AMPS)
100
75
9V
V
GS
= 10 V
8V
I D , DRAIN CURRENT (AMPS)
V
DS
≥
10 V
7V
6V
50
25
0
25°C
5V
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.016
0.014
0.012
0.010
25°C
0.008
0.006
0.004
−55
°C
T
J
= 25°C
V
GS
= 10 V
T
J
= 100°C
0.012
0.011
0.010
T
J
= 25°C
V
GS
= 10 V
0.009
0.008
0.007
0.006
15 V
0
25
50
75
100
125
150
0
25
50
75
100
125
150
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
R DS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
1.9
V
GS
= 10 V
I
D
= 37.5 A
1.6
1000
V
GS
= 0 V
T
J
= 125°C
I DSS, LEAKAGE (nA)
100
100°C
1.3
10
25°C
1
0.7
− 50
− 25
0
25
50
75
100
125
150
1
0
10
20
30
40
50
60
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTB75N06HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
7000
6000
C
iss
C, CAPACITANCE (pF)
5000
4000
3000
2000
C
oss
1000
C
rss
0
10
5
V
GS
0
V
DS
5
10
15
20
25
C
iss
C
rss
V
DS
= 0 V
V
GS
= 0 V
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
T
J
= 25°C
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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