CT2566
MIL-STD-1553 to Microprocessor
Interface Unit
Features
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•
•
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Second Source
Compatible to the
BUS-66300
PGA Version available, (second source to the BUS-66312)
Compatible with MIL-STD-1750 CPUs
Compatible with MOTOROLA, INTEL, and ZILOG CPUs
Compatible with Aeroflex’s CT2565 BC/RT/MT and CT2512 RT
Minimizes CPU overhead
Signal controls for shared memory implementation
Transfers complete messages to shared memory
Provides memory mapped 1553 interface
Packaging – Hermetic Metal
• 78 Pin, 2.1" x 1.87" x .25" PGA type package
• 82 Lead, 2.2" x 1.61 x .18" Flat Package
CIRCUIT TECHNOLOGY
www.aeroflex.com
A E
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ISO
9001
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RT
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Description
Aeroflex CT2566 MIL-STD-1553 to Microprocessor Interface Unit simplifies the CPU to 1553 Data
Bus interface. The CT2566 provides an interface by using RAM allowing the CPU to transmit or
receive 1553 traffic simply by accessing the memory. All 1553 message transfers are entirely
memory or I/O mapped. The CT2566 supports 1553 interface devices such as Aeroflex's CT2512
dual RT or the CT2565 dual BC, RT, and MT. The CT2566 operates over the full military -55°C to
+125°C temperature range.
CLOCK IN
MSTRCLR
SELECT
STRBD
READYD
RD/WR
MEM/REG
EXTEN
EXTLD
CPU
TIMING
MEMORY
TIMING
IOEN
BUSREQ
BUSGRNT
BUSACK
CS
OE
WR
MEMCS
MEMOE
MEMWR
ADRINC
NBGRNT
BCSTART
TAGEN
EOM
SOM
BLOCK
STATUS
WORD
MSGERR
TIMEOUT
STATERR
LOOPERR
CHB/CHA
CTLINB/A
CTLOUT B/A
RTU/BC
MT
DBAC
SSBUSY
SSFLAG
SVCREQ
RESET
CONTENTION
RESOLVER
MICROCODE
CONTROLLER
A15-A00
D15-D00
OPERATION
CONTROL
REGISTERS
CONFIGURATION
REGISTER
START / RESET
REGISTER
INTERRUPT
MASK
REGISTER
INT
INTERRUPT
GENERATOR
Figure 1 – Functional Block Diagram
eroflex Circuit T
echnology
– Data Bus Modules For The Future © SCDCT2566 REV B 8/10/99
PARAMETER
Specifications at Nominal Power Supply Voltages
VALUE
−
630
−
700
UNITS
Logic
I
IH
(With V
IH
= 2.7V)
I
IL
(With V
IL
= 0.0V)
I
OH
I
OL
V
IH
V
IL
V
OH
V
OL
Clock
Power Supplies
Voltage
Current Drain
Temperature Range
Operating (Case)
Storage
Physical Characteristics
Size
78 pin DIP
82 pin flatpack
Weight
78 pin DIP
82 pin flatpack
µA
µA
mA
mA
V
V
V
V
MHz
V
mA
°C
°C
4.0 min
4.0
2.0
0.8
3.7
0.4
12
5.0±10%
10 typ
−
55 to +125
−
65 to +150
2.1 x 1.87 x 0.25
(53 x 47.5 x 6.4)
2.1 x 1.87 x 0.25
(55.6 x 40.6 x 3.71)
1 (28)
1 (28)
in
(mm)
in
(mm)
oz (g)
oz (g)
Table 1 – Specifications
GENERAL
The CT2566 was designed to perform required
handshaking to the 1553 interface device, storing
or retrieving message(s) from a user supplied
RAM and notifying the CPU that a 1553
transaction has occurred. The CPU uses this
RAM to read the received data as well as to store
messages to be transmitted onto the Bus.
The CT2566 can be used to implement BC, RT,
or MT operation and can be either memory
mapped or I/O mapped to CPU address space.
Registers internal to the CT2566 control its
operation.
The CT2566 can access up to four external,
user supplied registers and can address up to
64K words of RAM. The RAM selected must be a
non-latched static RAM (capable of meeting the
timing constraints for the CT2566). A double
Aeroflex Circuit Technology
buffering architecture is provided to prevent
incomplete or partially updated information from
being transmitted onto the 1553 Data Bus.
The CT2566 requires an external, user supplied
clock.
COMPATIBLE MICROPROCESSOR TYPES
The CT2566 may be used with most common
microprocessors, including, the Motorola 68000
family, the Intel 8080 family, Zilog Z8000
products,
and
available
MIL-STD-1750
processors.
Interfacing the CT2566 to the 1553 Data Bus
requires external circuitry such as Aeroflex’s
CT2565(BC/RT/MT)
and
ACT4489D
transceivers. Figure 2 shows the interconnection
for these components.
2
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NAME
SELECT
RD/WR
READYD
EXTEN
TAGEN
EOM
SOM
STATERR
ADRINC
MEM/REG
CLOCK IN
LOOPERR
BUSREQ
BUSGRNT
I/O
I
I
O
O
O
I
I
I
I
I
I
I
I
O
DESCRIPTION
Select. When active, selects CT2566 for operation.
Read/Write. Controls CPU bus data direction.
Ready Data. When active indicates data has been received
from, or is available to the CPU.
External Enable. Output from CT2566 to enable output from
external devices. Same timing as MEMOE.
Tag Enable. Enables an external time tag counter for
transferring the time tag word into memory.
End of Message. Input from 1553 device indicating end of
message.
Start of Message. Input from 1553 device indicating start of
message in RTU mode.
Status Error. Input from 1553 device when status word has
either a bit set or unexpected RT address (in BC mode only).
Address Increment. Sent from 1553 device to increment
address counter following word transfer.
Memory/Register. Input from CPU to select memory or
register data transfer.
Clock input; 50% duty cycle, 12MHz, max.
Loop Error. Input from 1553 device if short loop BIT fails.
Bus Request. When active, indicates 1553 device requires
use of the address/data bus.
Bus Grant. Handshake output to 1553 device in response to
BUS REQUEST indicating address/data bus available to
1553 device.
-
Memory Chip Select. Low from CT2566 to enable external
RAM. Used with 4K x 4 RAM type device to read RAM or
used in conjunction with MEMWR to write data into RAM.
Output Enable. Input from 1553 device used to enable
memory on the parallel bus.
Not Used.
Low pulse from 1553 device preceding start of received new
protocol sequence. Used with superseding command to reset
DMA in progress.
Logic power supply.
Data Bus Bit 15 (MSB).
Data Bus Bit 13.
Data Bus Bit 11.
Data Bus Bit 9.
Data Bus Bit 7.
Data Bus Bit 5.
Data Bus Bit 3.
15
16
Not Used
MEMCS
-
O
17
18
19
OE
N/C
NBGRNT
I
-
I
20
21
22
23
24
25
26
27
+ 5 Volt
D15
D13
D11
D09
D07
D05
D03
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 2 – Pin Functions (78 Pin DIP)
3
Aeroflex Circuit Technology
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
PIN NO.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NAME
D01
SSFLAG
SSBUSY
RTU/BC
A14
A12
A10
A08
A06
A04
A02
A00
GND
STRBD
IOEN
I/O
I/O
O
O
O
O
O
O
O
O
O
I/O
I/O
-
I
O
DESCRIPTION
Data Bus Bit 1.
Subsystem Flag. Output to 1553 device to set RT subsystem
flag status bit.
Subsystem Busy. Output to 1553 device to set RT subsystem
busy flag.
Output to 1553 device used in conjunction with MT to set
operating mode.
Address Bit 14.
Address Bit 12.
Address Bit 10.
Address Bit 8.
Address Bit 6.
Address Bit 4.
Address Bit 2.
Address Bit 0 (LSB).
Signal Return.
Strobe Data. Used in conjunction with SELECT to indicate a
data transfer cycle to/from CPU.
Input/Output Enable. Output from CT2566 to enable external
buffers/latches connecting the hybrid to the address/data
bus.
External Load. Used to load data into external device via the
CT2566 data bus. Same timing as MEMWR.
Input from 1553 in RT mode used to indicate received 1553
message came in either Channel A or B.
Interrupt. Interrupt pulse line to CPU.
Bus Controller Start. Outputs to 1553 in initiate BC cycle.
Reset. Output to external device from CT2566 consisting of
the OR condition of CPU reset and CPU Master Clear.
Message Error. Input from 1553 device when an error occurs
in message sequence.
Input to change active memory map area (0 = area A).
Output from CT2566 selecting which area is to be active (0 =
area A).
Input from 1553 device indicating no response time-out.
Master Clear. Power-on reset from CPU. Resets DMA in
progress and internal registers to logic “0”.
Bus Acknowledge. Input from 1553 device acknowledge
receipt of BUSGRNT.
Write. Input from 1553 device for writing data into memory.
Chip Select. Input from 1553 device that is routed to
MEMCS.
43
44
45
46
47
48
49
50
51
52
53
54
55
EXTLD
CHB/CHA
INT
BCSTART
RESET
MSGERR
CTLIN B/A
CTLOUT B/A
TIMEOUT
MSTRCLR
BUSACK
WR
CS
O
O
O
O
I
I
O
I
I
I
I
I
Table 2 – Pin Functions (78 Pin DIP) (Cont.)
Aeroflex Circuit Technology
4
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
PIN NO.
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
NAME
MEMOE
MEMWR
Not Used
MT
D14
D12
D10
D08
D06
D04
D02
D00
SVCREQ
DBAC
A15
A13
A11
A09
A07
A05
A03
A01
GND
I/O
O
O
-
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I/O
-
DESCRIPTION
Memory Output Enable. Output from CT2566 to enable
memory output data.
Memory Write. Output pulse from CT2566 to write data bus
data into memory.
-
Bus Monitor. Used in conjunction with RTU/BC to set
operating mode.
Data Bus Bit 14.
Data Bus Bit 12.
Data Bus Bit 10.
Data Bus Bit 8.
Data Bus Bit 6.
Data Bus Bit 4.
Data Bus Bit 2.
Data Bus Bit 0 (LSB).
Service Request. Used to set service request bit in RT Status
Word.
Dynamic Bus Acceptance. Used to set status bit in RT Status
Word.
Address Bit 15 (MSB).
Address Bit 13.
Address Bit 11.
Address Bit 9.
Address Bit 7.
Address Bit 5.
Address Bit 3.
Address Bit 1.
Chassis Ground.
Table 2 – Pin Functions (78 Pin DIP) (Cont.)
PIN NO.
1
2
3
4
5
6
7
N/C
SELECT
STRBD
RD/WR
IOENBL
READYD
EXTLD
FUNCTION
PIN NO.
42
43
44
45
46
47
48
N/C
GROUND
CHASSIS GROUND
A00 (LSB)
A01
A02
A03
FUNCTION
Table 3 – CT2566FP Pin Functions (82 Pin Flat Package)
Aeroflex Circuit Technology
5
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
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