PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Dual differential 3.3V LVPECL outputs
•
Selectable crystal oscillator interface
or LVCMOS TEST_CLK
•
Output frequency up to 700MHz
•
Crystal input frequency range: 12MHz to 27MHz
•
VCO range: 250MHz to 700MHz
•
Parallel or serial interface for programming counter
and output dividers
•
RMS period jitter: 9ps (maximum)
•
Cycle-to-cycle jitter: 25ps (maximum)
•
3.3V supply voltage
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS8430BI-71 is a general purpose, dual out-
put Crystal/LVCMOS-to-3.3V Differential LVPECL
HiPerClockS™
High Frequency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8430BI-71 has a se-
lectable crystal oscillator interface or LVCMOS TEST_CLK.
The VCO operates at a frequency range of 250MHz to
700MHz. With the output configured to divide the VCO
frequency by 2, output frequency steps as small as 2MHz
can be achieved using a 16MHz crystal or test clock. Output
frequencies up to 700MHz can be programmed using the
serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430BI-71 make it an
ideal clock generator for most clock tree applications.
IC
S
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL_IN
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
TEST_CLK
0
M5
M6
M7
XTAL_IN
OSC
XTAL_OUT
÷
16
1
M8
N0
N1
N2
V
EE
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
XTAL_OUT
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
ICS8430BI-71
21
20
19
18
17
PLL
PHASE DETECTOR
VCO
÷
M
÷
2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
CONFIGURATION
INTERFACE
LOGIC
0
÷
N
1
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
MR
FOUT0
nFOUT0
FOUT1
nFOUT1
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
TEST
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430BYI-71
www.icst.com/products/hiperclocks.html
1
REV. A FEBRUARY 17, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the
parallel input mode. The relationship between the VCO fre-
quency, the crystal frequency and the M divider is defined as
follows: fVCO = fxtal x 2M
16
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defined as 125
≤
M
≤
350. The frequency
out is defined as follows: fout = fVCO = fxtal x 2M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8430BI-71 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crys-
tal, this provides a 1MHz reference frequency. The VCO of
the PLL operates over a range of 250MHz to 700MHz. The
output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjust-
ing the VCO control voltage. Note that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to
each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS8430BI-71 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial.
Fig-
ure 1
shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on inputs
M0 through M8 and N0 through N2 is passed directly to the M
divider and N output divider. On the LOW-to-HIGH transition
of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and N bits can
be hardwired to set the M divider and N output divider to a
T1
0
0
1
1
T0
0
1
0
1
TEST Output
LOW
S_Data clocked into register
Output of M divider
CMOS Fout
S
ERIAL
L
OADING
S_CLOCK
S_DATA
T1
t
S
T0
H
N2
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N2
nP_LOAD
M, N
t
S_LOAD
S
t
H
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
8430BYI-71
www.icst.com/products/hiperclocks.html
2
REV. A FEBRUARY 17, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Type
Input
Input
Input
Input
Power
Output
Power
Output
Power
Output
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 3,
28, 29, 30
31, 32
4
5, 6
7
8, 1 6
9
10
11, 12
13
14, 15
Name
M5, M6, M7,
M0, M1, M2,
M3, M4
M8
N0, N1
N2
V
EE
TEST
V
CC
FOUT1,
nFOUT1
V
CCO
FOUT0,
nFOUT0
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS / LVTTL interface levels.
Pullup
Pulldown Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
Pullup
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
Core power supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master reset. When logic HIGH, the internal dividers are
reset causing the true outputs (FOUTx) to go low and the inver ted
17
MR
Input
Pulldown outputs (nFOUTx) to go high. When Logic LOW, the internal dividers
and the outputs are enabled. Asser tion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
18
S_CLOCK
Input
Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
19
S_DATA
Input
Pulldown
S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
20
S_LOAD
Input
Pulldown
LVCMOS / LVTTL interface levels.
Power
Analog supply pin.
21
V
CCA
Selects between the cr ystal oscillator or test clock as the
PLL reference source. Selects XTAL inputs when HIGH.
22
XTAL_SEL
Input
Pullup
Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
Pulldown Test clock input. LVCMOS interface levels.
23
TEST_CLK
Input
Cr ystal oscillator interface. XTAL_IN is the input.
24,
XTAL_OUT,
Input
XTAL_OUT is the output.
25
XTAL_IN
Parallel load input. Determines when data present at M8:M0 is
26
nP_LOAD
Input
Pulldown loaded into the M divider, and when data present at N2:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
27
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
8430BYI-71
www.icst.com/products/hiperclocks.html
3
REV. A FEBRUARY 17, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
Conditions
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
X
X
L
L
↑
↓
L
H
MR
H
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
M
X
Data
Data
X
X
X
X
N
X
Data
Data
X
X
X
X
S_LOAD
L
H
X
X
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
VCO Frequency
(MHz)
250
252
254
256
•
•
696
M Divide
125
126
127
128
•
•
348
256
M8
0
0
0
0
•
•
1
128
M7
0
0
0
1
•
•
0
64
M6
1
1
1
0
•
•
1
32
M5
1
1
1
0
•
•
0
16
M4
1
1
1
0
•
•
1
8
M3
1
1
1
0
•
•
1
4
M2
1
1
1
0
•
•
1
2
M1
0
1
1
0
•
•
0
1
M0
1
0
1
0
•
•
0
1
0
698
349
1
0
1
0
1
1
1
0
700
35 0
1
0
1
0
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency of
16MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N2
0
0
0
0
1
1
1
1
8430BYI-71
N Divider Value
N0
0
1
0
1
0
1
0
1
2
4
8
16
1
2
4
8
N1
0
0
1
1
0
0
1
1
FOUT0, nFOUT0 Output Frequency
(MHz)
Minimum
Maximum
125
35 0
62.5
31.25
15.625
250
125
62.5
31.25
175
87.5
43.75
700
350
175
87.5
REV. A FEBRUARY 17, 2006
www.icst.com/products/hiperclocks.html
4
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430BI-71
700MH
Z
, L
OW
J
ITTER
, C
RYSTAL
I
NTERFACE
/
LVCMOS-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
140
15
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
TEST_CLK; NOTE 1
Input
VCO_SEL, S_LOAD, S_DATA,
High Voltage S_CLOCK, nP_LOAD, MR,
M0:M8, N0:N2, XTAL_SEL
Input Low Voltage
M0-M7, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD
Input
High Current M8, N2, XTAL_SEL, VCO_SEL
TEST_CLK
Input
Low Current
M0-M7, N0, N1, MR, nP_LOAD,
S_CLOCK, S_DATA, S_LOAD
TEST_CLK, M8, N2,
XTAL_SEL, VCO_SEL
Test Conditions
Minimum
2.35
2
-0.3
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
-150
2. 6
0.5
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
15 0
5
200
Units
V
V
V
µA
µA
µA
µA
µA
V
V
I
IL
Output
TEST; NOTE 2
High Voltage
Output
TEST; NOTE 2
V
OL
Low Voltage
NOTE 1: Characterized with 1ns input edge rate.
NOTE 2: Outputs terminated with 50
Ω
to V
CCO
/2.
V
OH
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
V
SWING
Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V. See "Parameter Measurement Information" section,
"3.3V Output Load Test Circuit" figure.
8430BYI-71
www.icst.com/products/hiperclocks.html
5
REV. A FEBRUARY 17, 2006
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