700MHz, Low Jitter, Crystal-to-3.3V
Differential LVPECL Frequency Synthesizer
ICS84330C
DATA SHEET
General Description
The ICS84330C is a general purpose, single output
high frequency synthesizer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The VCO operates at a frequency
range of 250MHz to 700MHz. The VCO and output
frequency can be programmed using the serial or parallel interfaces
to the configuration logic. The output can be configured to divide the
VCO frequency by 1, 2, 4, and 8. Output frequency steps as small as
250kHz to 2MHz can be achieved using a 16MHz crystal depending
on the output divider settings.
Features
•
•
•
•
•
•
•
•
•
•
•
Fully integrated PLL, no external loop filter requirements
One differential 3.3V LVPECL output
Crystal oscillator interface: 10MHz to 25MHz
Output frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming M and N dividers during
power-up
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
nFOUT
FOUT
V
CC
V
CC
V
EE
TEST
Pin Assignment
V
CC
32 31 30 29 28 27 26 25
S_CLOCK
S_DATA
S_LOAD
V
CCA
V
CCA
FREF_EXT
XTAL_SEL
XTAL1
1
2
3
4
5
6
7
8
9
XTAL2
V
EE
24
nc
N1
N0
M8
M7
M6
M5
M4
S_CLOCK
S_DATA
S_LOAD
V
CCA
FREF_EXT
XTAL_SEL
XTAL1
26
27
18
17
N1
N0
M8
M7
M6
M5
M4
ICS84330C
32 Lead VFQFN
K Package
5mm x 5mm x 0.925mm
package body
Top View
10 11 12 13 14 15 16
M2
M3
OE
nP_LOAD
M0
M1
nc
23
22
21
20
19
18
17
Pin Assignments
V
CC
nFOUT
25 24 23 22 21 20 19
ICS84330C
16
28
28 Lead PLCC
V Package
15
1
11.6mm x 11.4mm x 4.1mm
14
2
package body
Top View
13
3
4
5
XTAL2
FOUT
TEST
V
CC
V
EE
V
EE
Block Diagram
OE
XTAL1
OSC
XTAL2
FREF_EXT
Pulldown
Pullup
12
6
OE
7
nP_LOAD
8
M0
9
M1
10 11
M2
V
CC
TEST
M3
V
EE
1
FOUT
0
V
CC
nFOUT
÷ 16
XTAL_SEL
Pullup
32 31 30 29 28 27 26 25
PLL
PHASE DETECTOR
1
VCO
÷M
÷2
0
÷2
÷4
÷8
÷1
S_CLOCK
S_DATA
S_LOAD
FOUT
nFOUT
V
CCA
V
CCA
FREF_EXT
1
2
3
4
5
6
7
8
9
XTAL2
V
CC
V
EE
24
nc
N1
N0
M8
M7
M6
M5
M4
ICS84330C
32 Lead LQFP
Y Package
7mm x 7mm x 1.4mm
package body
Top View
23
22
21
20
19
18
17
M2
M3
OE
nP_LOAD
M0
M0:M8
N0:N1
Pullup
Pullup
ICS84330CV REVISION D JULY 17, 2009
1
©2009 Integrated Device Technology, Inc.
M1
nc
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
Pulldown
Pulldown
Pulldown
Pullup
XTAL_SEL
CONFIGURATION
INTERFACE
LOGIC
TEST
XTAL1
10 11 12 13 14 15 16
ICS84330C Data Sheet
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
The ICS84330C features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
quartz crystal is used as the input to the on-chip oscillator. The output
of the oscillator is divided by 16 prior to the phase detector. With a
16MHz crystal, this provides a 1MHz reference frequency. The VCO
of the PLL operates over a range of 250MHz to 700MHz. The output
of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency by adjusting the VCO
control voltage. Note that for some values of M (either too high or too
low), the PLL will not achieve lock. The output of the VCO is scaled
by a divider prior to being sent to each of the LVPECL output buffers.
The divider provides a 50% output duty cycle.
The programmable features of the ICS84330C support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial.
Figure 1
shows the timing
diagram for each mode. In parallel mode the nP_LOAD input is LOW.
The data on inputs M0 through M8 and N0 through N1 is passed
directly to the M divider and N output divider. On the LOW-to-HIGH
T2
0
0
0
0
1
1
1
1
T1
0
0
1
1
0
0
1
1
T0
0
1
0
1
0
1
0
1
transition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. The TEST output is Mode 000 (shift register out)
when operating in the parallel input mode. The relationship between
the VCO frequency, the crystal frequency and the M divider is defined
as follows:
fVCO = fXTAL x 2M
16
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock are defined as 125
≤
M
≤
350. The frequency out is defined as follows:
fout = fVCO = fXTAL x 2M
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are latched
on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
data at the S_DATA input is passed directly to the M divider on each
rising edge of S_CLOCK. The serial mode can be used to program
the M and N bits and test bits T2:T0. The internal registers T2:T0
determine the state of the TEST output as follows in the table below:
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
f
OUT
S_CLOCK ÷ N Divider
f
OUT
TEST Output
Shift Register Out
HIGH
PLL Reference XTAL ÷16
(VCO ÷ M)/2 (non 50% Duty Cycle M Divider)
f
OUT
, LVCMOS Output Frequency < 200MHz
LOW
(S_CLOCK ÷ M)/2 (non 50% Duty Cycle M Divider)
f
OUT
÷ 4
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T2
S
T1
H
T0
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
S_LOAD
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8, N0:N1
nP_LOAD
t
S
M, N
t
H
nP_LOAD
Time
Figure 1. Parallel & Serial Load Operations
ICS84330CV REVISION D JULY 17, 2009
2
©2009 Integrated Device Technology, Inc.
ICS84330C Data Sheet
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Name
V
CCA
XTAL1, XTAL2
XTAL_SEL
OE
nP_LOAD
M0, M1, M2
M3, M4, M5
M6, M7, M8
N0, N1
V
EE
TEST
V
CC
nFOUT, FOUT
nc
FREF_EXT
S_CLOCK
S_DATA
S_LOAD
Input
Input
Input
Pullup
Pullup
Pullup
Power
Type
Description
Analog supply pin.
Crystal oscillator interface. XTAL1 is an oscillator input, XTAL2 is an oscillator output.
Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW.
LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded into M divider, and
when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
Single-ended LVPECL interface levels.
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
No connect.
Pulldown
Pulldown
Pulldown
Pulldown
PLL reference input. LVCMOS / LVTTL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
Input
Pullup
Input
Power
Output
Power
Output
Unused
Input
Input
Input
Input
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
ICS84330CV REVISION D JULY 17, 2009
3
©2009 Integrated Device Technology, Inc.
ICS84330C Data Sheet
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
nP_LOAD
X
L
↑
H
H
H
H
H
M
X
Data
Data
X
X
X
X
X
N
X
Data
Data
X
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
H
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Conditions
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to the M divider and
N output divider. TEST mode 000.
Data is latched into input registers and remains loaded until next
LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on S_DATA on
each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider and
N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑
= Rising edge transition
↓
= Falling edge transition
Table 3B. Programmable VCO Frequency Function Table
VCO Frequency
(MHz)
250
252
254
256
•
•
696
698
700
256
M Divide
125
126
127
128
•
•
348
349
350
M8
0
0
0
0
•
•
1
1
1
128
M7
0
0
0
1
•
•
0
0
0
64
M6
1
1
1
0
•
•
1
1
1
32
M5
1
1
1
0
•
•
0
0
0
16
M4
1
1
1
0
•
•
1
1
1
8
M3
1
1
1
0
•
•
1
1
1
4
M2
1
1
1
0
•
•
1
1
1
2
M1
0
1
0
1
•
•
0
0
1
1
M0
1
0
1
0
•
•
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
Table 3C. Programmable Output DividerFunction Table
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
2
4
8
1
Output Frequency (MHz)
Minimum
125
62.5
31.25
250
Maximum
350
175
87.5
700
ICS84330CV REVISION D JULY 17, 2009
4
©2009 Integrated Device Technology, Inc.
ICS84330C Data Sheet
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
28 Lead PLCC
32 Lead LQFP
32 Lead VFQFN
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
37.8°C/W (0 lfpm)
47.9°C/W (0 lfpm)
37.0°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
CC
V
CCA
I
CC
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
160
16
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
M0-M8, N0, N1, OE,
nP_LOAD, XTAL_SEL
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
M0-M8, N0, n1, OE,
nP_LOAD, XTAL_SEL
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
I
IL
Input
Low Current
Table 4C. LVPECL DC Characteristics,
V
CC
= 3.3V±5%, V
EE
= 0V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CC
-2V.
ICS84330CV REVISION D JULY 17, 2009
5
©2009 Integrated Device Technology, Inc.
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