PRELIMINARY
DATA SHEET
Integrated
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL
™LVCMOS/C
ICS8422004I
Circuit
F
EMTO
C
LOCKS
RYSTAL
-
TO
-
Systems, Inc.
FREQUENCY SYNTHESIZER
LVHSTL F
REQUENCY
S
YNTHESIZER
ICS8422004I
G
ENERAL
D
ESCRIPTION
The ICS8422004I is a 4 output LVHSTL Synthesizer
optimized to generate Fibre Channel reference
HiPerClockS™
clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz and
53.125MHz. The ICS8422004I uses ICS’ 3
rd
generation low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS8422004I is packaged in a small
24-pin TSSOP package.
F
EATURES
• Four LVHSTL outputs (VOHmax = 1.2V)
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25, 106.25MHz, 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.59ps (typical)
• Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
IC
S
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input
Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
26.04166
23.4375
Inputs
M Divider N Divider
Value
Value
24
3
24
24
24
24
24
4
6
12
4
3
M/N
Divider Value
8
6
4
2
6
8
Output
Frequency
(MHz)
212.5
159.375
106.25
53.125
156.25
187.5
P
IN
A
SSIGNMENT
nQ1
Q1
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
DDO
Q3
nQ3
GND
nc
nXTAL_SEL
TEST_CLK
GND
XTAL_IN
XTAL_OUT
F_SEL1 F_SEL0
0
0
1
1
0
0
0
1
0
1
1
0
ICS8422004I
B
LOCK
D
IAGRAM
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
2
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Q0
Top View
1
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
TEST_CLK
Pulldown
26.5625MHz
nQ0
Q1
nQ1
1
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
0
Q2
nQ2
M = 24 (fixed)
Pulldown
Q3
nQ3
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8422004AGI
www.icst.com/products/hiperclocks.html
1
REV. B NOVEMBER 14, 2005
IDT™ / ICS™
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
1
ICS8422004I
PRELIMINARY
Integrated
ICS8422004I
Circuit
F
EMTO
C
LOCKS
™LVCMOS/C
RYSTAL
-
TO
-
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
TSD
Systems, Inc.
ICS8422004I
LVHSTL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 22
4, 5
6
Name
nQ1, Q1
V
DDO
Q0, nQ0
MR
Type
Output
Power
Ouput
Input
Description
Differential output pair. LVHSTL interface levels.
Output supply pins.
Differential output pair. LVHSTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Power supply ground.
Pulldown LVCMOS/LVTTL clock input.
Selects between cr ystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
7
8, 1 8
9
10, 12
11
13, 14
15, 19
16
17
20, 21
23, 24
nPLL_SEL
nc
V
DDA
F_SEL0,
F_SEL1
V
DD
XTAL_OUT,
XTAL_IN
GND
TEST_CLK
nXTAL_SEL
nQ3, Q3
Q2, nQ2
Input
Unused
Power
Input
Power
Input
Power
Input
Input
Output
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
8422004AGI
www.icst.com/products/hiperclocks.html
2
REV. B NOVEMBER 14, 2005
IDT™ / ICS™
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
2
ICS8422004I
PRELIMINARY
Integrated
ICS8422004I
Circuit
F
EMTO
C
LOCKS
™LVCMOS/C
RYSTAL
-
TO
-
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
TSD
Systems, Inc.
ICS8422004I
LVHSTL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
70°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
3.135
1.6
Typical
3.3
3.3
1.8
90
10
0
Maximum
3.465
3.465
2.0
Units
V
V
V
mA
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
2.375
1.6
Typical
2.5
2.5
1.8
80
10
0
Maximum
2.625
2.625
2.0
Units
V
V
V
mA
mA
mA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%
OR
2.5V±5%, V
DDO
= 1.8V±0.2V,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V
or 2.5V
V
DD
= 3.465V or 2.5V,
V
IN
= 0V
-150
Minimum Typical
2
1.7
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
I
IL
8422004AGI
µA
www.icst.com/products/hiperclocks.html
3
REV. B NOVEMBER 14, 2005
IDT™ / ICS™
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
3
ICS8422004I
PRELIMINARY
Integrated
ICS8422004I
Circuit
F
EMTO
C
LOCKS
™LVCMOS/C
RYSTAL
-
TO
-
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
TSD
Systems, Inc.
ICS8422004I
LVHSTL F
REQUENCY
S
YNTHESIZER
Minimum
1.0
0
40
0.6
Typical
Maximum
1. 2
0.4
60
1.1
Units
V
V
%
V
T
ABLE
3D. LVHSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
OX
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Test Conditions
Peak-to-Peak Output Voltage Swing
V
SWING
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
3E. LVHSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
OX
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
40
0.9
Test Conditions
Minimum
1.0
0.235
60
Typical
Maximum
1.2
Units
V
V
%
V
Peak-to-Peak Output Voltage Swing
V
SWING
NOTE 1: Outputs terminated with 50
Ω
to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
23.33
Test Conditions
Minimum
Typical
26.5625
Maximum
28.33
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
8422004AGI
www.icst.com/products/hiperclocks.html
4
REV. B NOVEMBER 14, 2005
IDT™ / ICS™
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
4
ICS8422004I
PRELIMINARY
Integrated
ICS8422004I
Circuit
F
EMTO
C
LOCKS
™LVCMOS/C
RYSTAL
-
TO
-
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
TSD
Systems, Inc.
ICS8422004I
LVHSTL F
REQUENCY
S
YNTHESIZER
Minimum
186.67
140
93.33
46.67
TBD
0.59
0.53
0.56
0.50
0.56
0.66
410
Typical
Maximum
226.66
170
113.33
56.66
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
t
sk(o)
Output Skew; NOTE 1, 3
212.5MHz, (637kHz - 10MHz)
187.5MHz, (637kHz - 10MHz)
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 2
159.375MHz, (637kHz - 10MHz)
156.25MHz, (1.875MHz - 20MHz)
106.25MHz, (1.875MHz - 20MHz)
53.125MHz, (637kHz - 10MHz)
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
t
sk(o)
Output Skew; NOTE 1, 3
212.5MHz, (637kHz - 10MHz)
187.5MHz, (637kHz - 10MHz)
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 2
159.375MHz, (637kHz - 10MHz)
156.25MHz, (1.875MHz - 20MHz)
106.25MHz, (1.875MHz - 20MHz)
53.125MHz, (637kHz - 10MHz)
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
Minimum
186.67
140
93.33
46.67
TBD
0.60
0.72
0.64
0.50
0.55
0.68
380
Typical
Maximum
226.66
170
113.33
56.66
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
%
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8422004AGI
www.icst.com/products/hiperclocks.html
5
REV. B NOVEMBER 14, 2005
IDT™ / ICS™
FEMTOCLOCKS™ LVCMOS/CRYSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
5
ICS8422004I
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
