Integrated
Circuit
Systems, Inc.
ICS87972I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS/LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
F
EATURES
•
Fully integrated PLL
•
14 LVCMOS/LVTTL outputs; (12)clocks, (1)feedback, (1)sync
•
Selectable crystal oscillator interface or LVCMOS/LVTTL
reference clock inputs
•
CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
Output frequency range: 10MHz to 150MHz
•
VCO range: 240MHz to 500MHz
•
Output skew: 200ps (maximum)
•
Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
•
Full 3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Pin compatible with MPC972
•
Compatible with PowerPC™ and Pentium™ Microprocessors
G
ENERAL
D
ESCRIPTION
ICS
HiPerClockS™
The ICS87972I-147 is a low skew, LVCMOS/LVTTL
Clock Generator and a member of the HiPerClock™
S
family of High Performance Clock Solutions from
ICS.The ICS87972I-147 has three selectable inputs
and provides 14 LVCMOS/LVTTL outputs.
The ICS87972I-147 is a highly flexible device. Using the crystal
oscillator input, it can be used to generate clocks for a system.
All of these clocks can be the same frequency or the device can
be configured to generate up to three different frequencies among
the three output banks. Using one of the single ended inputs, the
ICS87972I-147 can be used as a zero delay buffer/multiplier/
divider in clock distribution applications.
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. The output
frequency range is
10MHz
to 150MHz. Input frequency range is
6MHz to 150MHz.
The ICS87972I-147 also has a QSYNC output which can be
used or system synchronization purposes. It monitors Bank A
and Bank C outputs and goes low one period
of the faster clock
prior to coincident rising edges of Bank A and Bank C clocks.
QSYNC then goes high again when the coincident rising edges
of Bank A and Bank C occur. This feature is used primarily in
applications where Bank A and Bank C are running at different
frequencies, and is particularly useful when they are running at
non-integer multiples of one another.
Example Applications:
1.
System Clock generator:
Use a 16.66 MHz Crystal to
generate eight 33.33MHz copies for PCI and four 100MHz
copies for the CPU or PCI-X.
2.
Line Card Multiplier:
Multiply 19.44MHz from a back plane
to 77.76MHz for the line Card ASICs and Serdes.
3.
Zero Delay buffer for Synchronous memory:
Fan out up
to twelve 100MHz copies from a memory controller ref-
erence clock to the memory chips on a memory module
with zero delay.
P
IN
A
SSIGNMENT
FSEL_FB0
EXT_FB
GNDO
GNDO
GNDO
V
DDO
V
DDO
QB0
QB1
QB2
QB3
QFB
V
DD
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
V
DDO
QA2
GNDO
QA1
V
DDO
QA0
GNDO
VCO_SEL
39 38 37 36 35 34 33 32 31 30 29 28 27
40
26
41
42
43
44
45
46
47
48
49
50
51
52
1
GNDI
FSEL_FB1
QSYNC
GNDO
QC0
V
DDO
QC1
FSEL_C0
FSEL_C1
QC2
V
DDO
QC3
GNDO
INV_CLK
25
24
23
22
21
ICS87972I-147
20
19
18
17
16
15
2
nMR/OE
3
FRZ_CLK
4
FRZ_DATA
5 6
FSEL_FB2
PLL_SEL
7 8
REF_SEL
CLK_SEL
14
9 10 11 12 13
CLK0
CLK1
XTAL1
XTAL2
V
DDA
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
87972DYI-147
www.icst.com/products/hiperclocks.html
1
REV. A FEBRUARY 24, 2009
Integrated
Circuit
Systems, Inc.
ICS87972I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS/LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
Type
Power
Input
Input
Input
Input
Description
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5, 26, 27
Name
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
PLL_SEL
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs. When
Pullup LOW, resets the outputs to tristate and resets output divide circuitr y.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
Pullup Clock input for freeze circuitr y. LVCMOS / LVTTL interface levels.
Configuration data input for freeze circuitr y.
Pullup
LVCMOS / LVTTL interface levels.
Pullup
Select pins control Feedback Divide value.
LVCMOS / LVTTL interface levels.
6
Input
7
8
9, 10
11, 12
13
14
15, 24, 30,
35, 39, 47, 51
16, 18, 21, 23
17, 22, 33
37, 45, 49
19, 20
25
28
29
31
32, 34, 36, 38
40, 41
42, 43
44, 46, 48, 50
52
REF_SEL
CLK_SEL
CLK0, CLK1
XTAL1,
XTAL2
V
DDA
INV_CLK
GNDO
QC3, QC2,
QC1, QC0
V
DDO
FSEL_C1,
FSEL_C0
QSYNC
V
DD
QFB
EXT_FB
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
VCO_SEL
Input
Input
Input
Input
Power
Input
Power
Output
Power
Input
Output
Power
Output
Input
Output
Input
Input
Output
Input
Selects between the PLL and reference clocks as the input to the output
Pullup dividers. When HIGH, selects PLL. When LOW, bypasses the PLL and
reference clocks. LVCMOS / LVTTL interface levels.
Selects between cr ystal and reference clock.
Pullup When LOW, selects CLK0 or CLK1. When HIGH, selects cr ystal inputs.
LVCMOS / LVTTL interface levels.
Clock select input. When LOW, selects CLK0.
Pullup
When HIGH, selects CLK1. LVCMOS / LVTTL interface levels.
Pullup Reference clock inputs. LVCMOS / LVTTL interface levels.
Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Analog supply pin.
Pullup
Inver ted clock select for QC2 and QC3 outputs.
LVCMOS / LVTTL interface levels.
Power supply ground.
Bank C clock outputs. 7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins.
Pullup Select pins for Bank C outputs. LVCMOS / LVTTL interface levels.
Synchronization output for Bank A and Bank C. Refer to Figure 1,
Timing Diagrams. LVCMOS / LVTTL interface levels.
Core supply pins.
Feedback clock output. LVCMOS / LVTTL interface levels.
Pullup External feedback. LVCMOS / LVTTL interface levels.
Bank B clock outputs.7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels.
Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels.
Bank A clock outputs.7
Ω
typical output impedance.
LVCMOS / LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1.
Pullup
When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.
NOTE:
Pullup
refers to internal input resistors. See table 2, Pin Characteristics, for typical values.
87972DYI-147
www.icst.com/products/hiperclocks.html
4
REV. A FEBRUARY 24, 2009
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