PHY (TC-PMD) for 25.6 Mbps
ATM Networks
IDT77105
Features List
!
Description
The IDT77105 is a member of IDT's family of products developed to
support Asynchronous Transfer Mode (ATM) data communications and
networking. The IDT77105 provides the Transmission Convergence
(TC) and (PMD) layers of a 25.6 Mbps ATM PHY suitable for ATM
networks using Unshielded Twisted Pair (UTP) Category 3 (or better)
wiring. The UTOPIA interface provides standardized control and
communications to other components, such as Segmentation and Reas-
sembly (SAR) controllers and ATM switches.
The IDT77105 supports a simple interface to magnetics modules.
The IDT77105 is fabricated using IDT's state-of-the-art CMOS tech-
nology, providing the highest levels of integration, performance and reli-
ability, with the low-power consumption characteristics of CMOS.
!
!
!
!
!
!
!
!
!
!
!
Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions for
25.6 Mpbs ATM Networks
Performs clock/data recovery, serializing/deserializing &
framing
ITU-T I.432 and I.432.5 compliant
ATM Forum af-phy-0040 compliant
UTOPIA Level 1 Interface
2-Cell Transmit & Receive FIFOs
Supports Multi PHY Connections
LED Interface for status signalling
Supports UTP Category 3 (CAT 3) physical media
Interfaces to standard magnetics
Low-Power CMOS
64-pin STQFP Package (10 x 10mm)
Block Diagram
TxLED
TxRef
TxCLK
TxDATA
TxSOC
TxENB
TxFul
/CLAV
l
9
2 CELL FIFO
SCRAMBLER
4B/5B
ENCODER
P/S
NRZI
Line
Driver
TXD+
TXD-
PRNG
ALE
W RB
RD B
CS
ADDR/DATA
I
NT
RESET
UPLO
8
UTILITY
BUS
CONTROLLER
RESET
LOOP BACK
RxCLK
RxDATA
RxSOC
R xEnb
RxEm pt
y/CLAV
RxRef
9
2 CELL FIFO
DESCRAMBLER
5B/4B
DECODER
S/P
DNRZI
CLK
REC
Line
RxVR
RxD+
RxD-
77105
RxLED
PLL_Filter_2
TxOSC
PLL_Filter_1
3445 drw 00
1 of 24
2000 Integrated Device Technology, Inc.
September 11, 2000
DSC 3445
IDT77105
Pin Configurations
A LE
W RB
V cc
RDB
V cc
RXD+
V cc
R XD-
V cc
DNC
U P LO
P LL_F ilter_2
R X LE D
T X LE D
P LL_F ilter_1
TX D -
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
Index M ark
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CS
GND
AD0
AD1
AD2
AD3
AD4
AD5
V cc
AD6
AD7
I T
N
R ESET
TX R EF
TX D A TA 0
TX D A TA 1
TX D A TA 2
TX D A TA 3
TX D A TA 4
TX D A TA 5
TX D A TA 6
TX D A TA 7
T X P A R IT Y
T X C LK
TXENB
TXS O C
TXFULL/T X C LA V
RXENB
R X C LK
R X P A R IT Y
R X D ATA7
R X D ATA6
DNC
TXD +
GND
TXO SC
GND
RXSO C
R X EM PTY /R X C L A V
R XR E F
V cc
R XD ATA0
R X D A TA 1
R XD ATA2
R XD ATA3
R XD ATA4
R XD ATA5
GND
Logo
P a rt N u m b e r
D a te C o d e
2 of 24
344 5 d rw 01
September 11, 2000
IDT77105
Package Dimensions
64
1
A1
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
Rating
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
DC Output Current
Value
Unit
-0.5 to +7.0 V
-55 to +125
°C
-55 to +120
°C
50
mA
64-Pin
STQFP
PP64
T
STG
4.3514 '
E1
5.4035 '
E
I
OUT
2.4792 '
4.3021 '
D1
D
A
Note:
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
5.3521 '
Draft Angle = 11° - 13°
Recommended DC Operating
Conditions
A2
Symbol
.
Parameter
Digital Supply Voltage
Digital Ground Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.0
GND-0.3V
Max.
5.5
0
V
cc
+ 0.3V
0.8
Unit
V
V
V
V
A1
e
0.20 Rad Typ.
4.3514 '
V
cc
GND
V
IH
V
IL
E1
5.4035 '
E
0.20 Rad Typ.
4° ± 4°
2.4792 '
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Ambient Temperature
0°C to +70°C
-40°C to +85°C
GND
0V
0V
Unit
5.0V ± 0.5V
5.0V ± 0.5V
A
L
b
3445 drw 02
Industrial
Dimensions
Dimension Letter Tolerance (mm) Dimension (mm)
A
A1
A2
D
D1
E
E1
L
e
b
Max.
±.05
±.05
±.10
±.10
±.10
±.10
±15
Basic
05
1.60
0.10
1.40
12.00
10.00
12.00
10.00
0.60
0.50
0.22
DC Electrical Characteristics
Symbol
I
LI
1
I
LO2
V
OH
V
OL
I
DDI3
1.
2.
0.4V
3.
Parameter
Input Leakage Current (any input)
Output Leakage Current
Min.
-1
-10
Max.
1
10
—
0.4
100
Unit
µA
µA
V
V
mA
Output Logic “1” Voltage, I
OH
= -2mA 2.4
Output Logic “0” Voltage, I
OL
= 8mA
Active Power Supply Current
≤
VOUT
≤
VCC.
—
—
Measurements with 0.4V
≤
V
IN
≤
V
CC
.
Tested at f = 32MHz with outputs unloaded. Add 13mA additional current when TxD
outputs are driving a typical load.
3 of 24
September 11, 2000
IDT77105
Output Parameters for Transmit Line Signal @ Vcc = 5V ± 10%
Symbol
Voh
Vol
Ioh
Iol
Z
OUT
Parameter
Output Low Voltage for Transmit Line Signal, Ioh = 8mA —
Output High Current for Transmit Line Signal
Output Low Current for Transmit Line Signal
Output Impedance
—
—
—
Min.
Typ.
—
80
75
20
Max.
—
0.5
—
—
—
Unit
V
V
mA
mA
Ohm
Output High Voltage for Transmit Line Signal, Ioh = 8mA Vcc - 0.5V —
Input Parameters for IDT77105 Receive Line Signal
Symbol
I
LI
C
IN
1.
2.
Parameter
Input Leakage Current
1
Input Capacitance
2
-1
—
Min.
Typ.
—
—
Max.
1
10
Unit
µA
pF
Input Voltage = 2.5V (typ) ± 600mV
Measured with f=1MHz
+25°C,
Capacitance (T
A
= +25 C, f = 1MHz)
Symbol
C
IN1
C
OUT
1
1.
Parameter
Output Capacitance
Input Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
10
Unit
pF
pF
Characterized values, not currently tested.
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
ALE
WRB
V
CC
RDB
V
CC
RxD+
VCC
RxD-
V
CC
DNC
UPLO
PLL_Filter_2
RxLED
TxLED
PLL_Filter_1
TXD–
DNC
TxD+
GND
TxOsc
GND
Name
I
I
—
I
—
I
—
I
—
—
O
—
O
O
—
O
O
O
—
I
—
N/A
User defined
Discrete Capacitor
LED
LED
Discrete Capacitor
Magnetics
N/A
Magnetics
Ground plane
OSC
Ground plane
Table 1 Pin Description (Part 1 of 2)
4 of 24
September 11, 2000
Input from an external clock oscillator. 32MHz for 25.6 Mbps; ±100ppm
Magnetics
Magnetics
I/O
Interfaces to
Utility bus
Utility bus
Power Plane
Utility bus
Read Byte Enable (active low).
Reserved input
Positive Differential receive serial data input.
Reserved input
Negative Differential receive serial data input.
Reserved input
NOTE: This pin should float.
User Programmed Latched Output of Reg 0, bit 7 (opposite polarity).
(See Figure 20).
LED driver output (see Figure 8). Pulses low when a cell is being received.
LED driver output (see Figure 8). Pulses low when a cell is being transmitted
(See Figure 20).
Differential Negative transmit serial data output.
NOTE: This pin should float.
Differential Positive transmit serial data output.
Write Byte Enable (active low).
Description
Address Latch Enable signal. The falling edge of ALE is used to latch the address on AD[7:0].
IDT77105
Pin
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
RxSOC
RxEmpty/RxClav
RxRef
V
CC
RxData0
RxData1
RxData2
RxData3
RxData4
RxData5
GND
RxData6
RxData7
RxParity
RxClk
RxEnb
TxFull/TxCLAV
TxSOC
TxEnb
TxClk
TxParity
TxData7
TxData6
TxData5
TxData4
TxData3
TxData2
TxData1
TxData0
TxRef
Reset
INT
AD7
AD6
VCC
AD5
AD4
AD3
AD2
AD1
AD0
GND
CS
I/O
O
O
O
—
O
O
O
O
O
O
—
O
O
O
I
I
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
—
I
Interfaces to
UTOPIA bus
UTOPIA bus
UTOPIA bus
Power plane
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
Ground plane
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
UTOPIA bus
control
control
Utility bus
Utility bus
Power plane
Utility bus
Utility bus
Utility bus
Utility bus
Utility bus
Utility bus
Ground plane
Utility bus
Utility Bus Chip select (active low).
Table 1 Pin Description (Part 2 of 2)
5 of 24
September 11, 2000
Address/Data bit 5. Not used for addressing.
Address/Data bit 4. Not used for addressing.
Address/Data bit 3. Not used for addressing.
Address/Data bit 2.
Address/Data bit 1.
Address/Data bit 0.
Receive data bit 6.
Receive data bit 7.
Parity bit for RxData[7:0].
Receive data path synchronization clock.
Receive Enable signal (active low).
Transmit Full (active low; byte mode) or Transmit Cell Available (active high; cell mode).
Transmit Start of Cell signal.
Transmit Enable signal (active low).
Transmit data path synchronization clock.
Parity bit for TxData[7:0]. If unused, this pin must be tied high or low.
Transmit data bit 7.
Transmit data bit 6.
Transmit data bit 5.
Transmit data bit 4.
Transmit data bit 3.
Transmit data bit 2.
Transmit data bit 1.
Transmit data bit 0.
Transmit Reference signal input (active low). Assertion (falling edge) of this pin stimulates insertion of com-
mand byte X_8 into the transmit data stream.
Reset signal (active low).
Interrupt signal (active low). Always driven.
Address/Data bit 7. Not used for addressing.
Address/Data bit 6. Not used for addressing.
Receive data bit 0.
Receive data bit 1.
Receive data bit 2.
Receive data bit 3.
Receive data bit 4.
Receive data bit 5.
Receive Start of Cell signal.
Receive Empty (active low; byte mode) or Receive Cell Available (active high; cell mode).
Receive Reference signal (active low). This pin is driven in response to a received X_8 command byte.
Assertion duration is programmable to 1,2,4 or 8 clocks, as set via register 0x03, bits 3,4.
Description
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
