4 RX inputs—32 channels at 64 Kbit/s per serial line
4 TX output—32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
5V Power Supply
Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 40-pin
Plastic Dip (P-DIP) and 44-pin Plastic Quad Flatpack (PQFP)
°
°
Operating Temperature Range -40°C to +85°C
outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form
a multiplexed 2.048 Mb/s stream.
.UNCTIONAL DESCRIPTION
A functional block diagram of the IDT728981 device is shown below. The
serial streams operate continuously at 2.048 Mb/s and are arranged in 125µs
wide frames each containing 32, 8-bit channels. Four input (RX0-3) and four
output (TX0-3) serial streams are provided in the IDT728981 device allowing
a complete 128 x 128 channel non-blocking switch matrix to be constructed.
The serial interface (C4i) clock for the device is 4.096 MHz.
The received serial data is internally converted to a parallel format by the on
chip serial-to-parallel converters and stored sequentially in a 128-position Data
Memory. By using an internal counter that is reset by the input 8 KHz frame pulse,
F0i,
the incoming serial data streams can be framed and sequentially ad-
dressed.
DESCRIPTION:
The IDT728981 is a ST-BUS
®
compatible digital switch controlled by a
microprocessor. The IDT728981 can handle as many as 128, 64 Kbit/s input
and output channels. Those 128 channels are divided into 4 serial inputs and
.UNCTIONAL BLOCK DIAGRAM
C4i
F0i
V
CC
GND
ODE
Timing
Unit
RX0
RX1
RX2
RX3
Output MUX
TX0
Receive
Serial Data
Streams
Data
Memory
Control Register
Connection
Memory
Transmit
Serial Data
Streams
TX1
TX2
TX3
Microprocessor Interface
5703 drw01
DS
CS
R/W A0/
DTA
D0/
A5
D7
JANUARY 2001
1
2001 Integrated Device Technology, Inc.
DSC-5703/1
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
C
ommercial Temperature Range
PIN CON.IGURATION
DTA
DNC
(1)
DNC
(1)
DNC
(1)
DNC
(1)
DNC
(1)
ODE
RX1
DTA
RX2
RX0
ODE
TX0
RX0
RX1
TX0
TX1
TX2
INDEX
INDEX
44
41
39
43
42
38
40
37
36
2
35
44
43
42
41
RX3
V
CC
V
CC
V
CC
V
CC
V
CC
F0i
C4i
A
0
A
1
A
2
1
40
7
8
9
10
11
12
13
14
15
16
17
21
20
22
39
38
37
36
35
34
33
32
31
30
29
TX3
DNC
(1)
DNC
(1)
DNC
(1)
DNC
D
0
D
1
D
2
D
3
D
4
(1)
RX3
V
CC
V
CC
V
CC
V
CC
V
CC
F0i
C4i
A
0
A
1
A
2
34
6
4
5
3
DNC
(1)
RX2
TX1
TX2
1
2
3
4
5
6
7
8
9
10
11
12
15
17
13
14
18
16
19
20
21
22
33
32
31
30
29
28
27
26
25
24
23
TX3
DNC
(1)
DNC
(1)
DNC
(1)
DNC
(1)
GND
D
0
D
1
D
2
D
3
D
4
GND
23
24
25
26
18
19
27
28
DTA
5703 drw02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
5703 drw04
DNC
(1)
CS
D
7
D
6
DNC
(1)
DS
R/W
D
5
A
3
A
4
A
5
DNC
(1)
5703 drw03
DNC
(1)
D
7
D
6
DS
R/W
CS
D
5
A
3
A
4
A
5
DNC
(1)
RX0
RX1
RX2
ODE
TX0
TX1
TX2
TX3
DNC
(1)
DNC
(1)
DNC
(1)
DNC
(1)
GND
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CS
PLCC: 0.05in. pitch, 0.65in. x 0.65in.
(J44-1, order code: J)
TOP VIEW
RX3
V
CC
V
CC
V
CC
V
CC
V
CC
F0i
C4i
A
0
A
1
A
2
PQFP: 0.80mm pitch, 10mm x 10mm
(DB44-1, order code: DB)
TOP VIEW
NOTE:
1. DNC - Do Not Connect
A
3
A
4
A
5
DS
R/W
PIN DESCRIPTIONS
SYMBOL
GND
V
CC
PLASTIC DIP: 0.10in. pitch, 2.05in. x 0.60in.
(P40-1, order code: P)
TOP VIEW
NAME
Ground.
V
CC
Data Acknowledgment
(Open Drain)
RX Input 0 to 3
Frame Pulse
Clock
Address 0 to 5
Data Strobe
Read/Write
Chip Select
Data Bus 0 to 7
TX Outputs 0 to 3
(Three-state Outputs)
Output Drive Enable
I/O
DESCRIPTION
Ground Rail.
+5.0 Volt Power Supply.
This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this
output.
Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s.
This input identifies frame synchronization signals formatted to ST-BUS
®
specifications.
4.096 MHz serial clock for shifting data in and out of the data streams.
These lines provide the address to IDT728981 internal registers.
This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with
CS
to enable the internal read and write generation.
This input controls the direction of the data bus lines (D0-D7) during a microprocessor access.
Active LOW input enabling a microprocessor read or write of control register or internal memories.
These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH,
Connection Memory LOW and data memory.
Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s.
This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is
HIGH, each channel may still be put into high-impedance by software control.
2
DTA
RX0-3
O
I
I
I
I
I
I
I
I/O
O
I
F0i
C4i
A0-A5
DS
R/W
CS
D0-D7
TX0-3
ODE
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
C
ommercial Temperature Range
modes such as: Processor mode or Connection mode and Output Drivers
Enabled or in three-state condition.
OUTPUT DRIVE ENABLE (ODE)
The ODE pin is the master three-state output control pin. If the ODE input
is held LOW all TX outputs will be placed in high impedance regardless
Connection Memory High programming. However, if ODE is HIGH, the contents
of Connection Memory High control the output state on a per-channel basis.
DELAY THROUGH THE IDT728981
The transfer of information from the input serial streams to the output serial
streams results in a delay through the device. The delay through the IDT728981
device varies according to the combination of input and output streams and the
movement within the stream from channel to channel. Data received on an input
stream must first be stored in Data Memory before it is sent out.
As information enters the IDT728981 it must first pass through an internal
serial-to-parallel converter. Likewise, before data leaves the device, it must
pass through the internal parallel-to-serial converter. This data preparation has
an effect on the channel positioning in the frame immediately following the
incoming frame—mainly, data cannot leave in the same time slot. Therefore,
information that is to be output in the same channel position as the information
is input, relative to the frame pulse, will be output in the following frame.
Whether information can be output during a following timeslot after the
information entered the IDT728981 depends on which RX stream the channel
information enters on and which TX stream the information leaves on. This is
caused by the order in which input stream information is placed into Data Memory
and the order in which stream information is queued for output. Table 1 shows the
allowable input/output stream combinations for the minimum two channel delay.
.UNCTIONAL DESCRIPTION (Cont'd)
Data to be output on the serial streams may come from two sources: Data
Memory or Connection Memory. The Connection Memory is 16 bits wide and
is split into two 8-bit blocks—Connection Memory HIGH and Connection
Memory LOW. Each location in Connection Memory is associated with a
particular channel in an output stream so as to provide a one-to-one correspon-
dence between Connection and Data Memories. This correspondence allows
for per channel control for each TX output stream.
In Processor Mode, data output on the TX is taken from the Connection
Memory Low and originates from the microprocessor (Figure 2). Where as in
Connection Mode (Figure 1), data is read from Data Memory using the address
in Connection Memory. Data destined for a particular channel on the serial
output stream is read during the previous channel time slot to allow time for
memory access and internal parallel-to-serial conversion.
CONNECTION MODE
In Connection Mode, the addresses of input source for all output channels
are stored in the Connection Memory Low. The Connection Memory Low
locations are mapped to corresponding 8-bit x 32-channel output. The contents
of the Data Memory at the selected address are then transferred to the parallel-
to-serial converters. By having the output channel to specify the input channel
through the Connection Memory, input channels can be broadcast to several
output channels.
PROCESSOR MODE
In Processor Mode the CPU writes data to specific Connection Memory Low
locations which are to be output on the TX streams. The contents of the
Connection Memory Low are transferred to the parallel-to-serial converter one
channel before it is to be output and are transmitted each frame to the output until
it is changed by the CPU.
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
functions available in the IDT728981. Output channels are selected into specific
Input
0
1
Output Stream
1,2,3
3
RX
Receive
Serial Data
Streams
Data
Memory
Connection
Memory
Table 1. Input Stream to Output Stream Combinations that can Provide the
Minimum 2-Channel Delay
Transmit
Serial Data
Streams
TX
5703 drw05
Figure 1. Connection Mode
A5 A4 A3 A2 A1 A0
0
1
1
1
·
1
1
X
0
0
•
•
•
HEX ADDRESS
00-1F
20
21
•
•
•
LOCATION
Control Register
(1)
Channel 0
(2)
Channel 1
(2)
•
•
•
X
0
0
•
•
•
X
0
0
•
•
•
0
0
0
•
•
•
0
0
1
•
•
•
Receive
Serial Data
Streams
Data
Memory
Connection
Memory
Transmit
Serial Data
Streams
TX
1
1
1
1
1
3F
Channel 31
(2)
5703 drw06
Microprocessor
NOTES:
1. Writing to the Control Register is the only fast transaction.
2. Memory and stream are specified by the contents of the Control Register.
Table 2. Address Mapping
Figure 2. Processor Mode
3
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
C
ommercial Temperature Range
If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
the CML define the source information (stream and channel) of the time slot that
is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) the output stream and channel.
INITIALIZATION OF THE IDT728981
On initialization or power up, the contents of the Connection Memory High
can be in any state. This is a potentially hazardous condition when multiple TX
outputs are tied together to form matrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
During the microprocessor initialization routine, the microprocessor should
program the desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two connected TX
outputs drive the bus simultaneously. With the CMH setup, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
SO.TWARE CONTROL
If the A5 address line input is LOW then the IDT728981 Internal Control
Register is addressed. If A5 input line is high, then the remaining address input
lines are used to select the 32 possible channels per input or output stream. The
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT728981 Data and
Connection memories. The IDT728981 memory mapping is illustrated in Table
2 and Figure 3.
The data in the control register (Table 3) consists of Memory Select and
Stream Address bits, Split Memory and Processor Mode bits. In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory as specified by the Memory Select Bits (Bits 4
and 3 of the Control Register). The Memory Select bits allow the Connection
Memory HIGH or LOW or the Data Memory to be chosen, and the Stream
Address bits define internal memory subsections corresponding to input or
output streams.
The Processor Enable bit (bit 6) places EVERY output channel on every
output stream in Processor mode; i.e., the contents of the Connection Memory
LOW (CML, see Table 5)) are output on the TX output streams once every frame
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT728981 behaves
as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection
Memory High (CMH) locations were set to HIGH, regardless of the actual value.
Control Register
CR
b
7
CR
b
6
CR
b
5
CR
b
4
CR
b
3
CR
b
2
CR
b
1
CR
b
0
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
stream.
CR
b
4
0
1
1
CR
b
3
1
0
1
Connection Memory High
Connection Memory Low
Data Memory
Channel 0
Channel 0
Channel 0
Channel 0
Channel 1
Channel 1
Channel 1
Channel 1
Channel 2
Channel 2
Channel 2
Channel 2
Channel 31
Channel 31
Channel 31
Channel 31
CR
b
1
0
0
1
1
CR
b
0 Stream
0
1
0
1
0
1
2
3
100000
100001
100010
111111
External Address Bits
A5-A0
5703 drw07
Figure 3. Address Mapping
4
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
C
ommercial Temperature Range
Mode Control
Bits
Memory Select
Stream Address
(unused)
Bits
(unused)
Bits
7
6
5
4
3
2
1
0
Bit
7
Name
SM (Split Memory)
Description
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except
when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the
operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.
When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE
pin is LOW. When 0, the Connection Memory bits for each channel determine what is output.
unused
0-0 - Not to be used.
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory LOW
1-1 - Connection Memory is HIGH
unused
The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the
subsection of memory made accessible for subsequent operations.
Table 3. Control Register Configuration
6
5
4-3
PE (Processor Mode)
MS1-MS0
(Memory Select Bits)
2
1-0
STA1-0
(Stream Address Bits)
No Corresponding Memory
- These bits give 0s if read
CS
(unused)
OE
7
6
5
4
3
2
1
0
Bit
2
Name
CS (Channel Source)
Description
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel
and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the
Data Memory and determine the source of the connection to the location's channel and stream.
unused
If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's
channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing
switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
Table 4. Connection Memory High Register
1
0
OE (Output Enable)
Stream Address
(unused)
Bits
Channel Address Bits
7
6
5
4
3
2
1
0
Bit
7
Name
unused
Description
The number expressed in binary notation on these 2 bits are the number of the stream for the source of the connection.
Bit 6 is the most significant bit, e.g., If bit 6 is 1, bit 5 is 0 then the source of the connection is a channel on RX2.
The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the
connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4
is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
6-5
(1)
Stream Address Bits
4-0
(1)
Channel Address Bits
NOTE:
1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with
this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.
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