19-2916; Rev 1; 10/03
KIT
ATION
EVALU
E
BL
AVAILA
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
General Description
Features
o
Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
o
Ultra-Low Power
75.6mW at f
CLK
= 40MHz (Transceiver Mode)
64mW at f
CLK
= 22MHz (Transceiver Mode)
Low-Current Idle and Shutdown Modes
o
Excellent Dynamic Performance
48.4dB SINAD at f
IN
= 5.5MHz (ADC)
70dB SFDR at f
OUT
= 2.2MHz (DAC)
o
Excellent Gain/Phase Match
±0.2°
Phase,
±0.05dB
Gain at f
IN
= 5.5MHz (ADC)
o
Internal/External Reference Option
o
+1.8V to +3.3V Digital Output Level (TTL/CMOS
Compatible)
o
Multiplexed Parallel Digital Input/Output for
ADCs/DACs
o
Miniature 48-Pin Thin QFN Package (7mm
✕
7mm)
o
Evaluation Kit Available (Order MAX5865EVKIT)
MAX5865
The MAX5865 ultra-low-power, highly integrated analog
front end is ideal for portable communication equipment
such as handsets, PDAs, WLAN, and 3G wireless termi-
nals. The MAX5865 integrates dual 8-bit receive ADCs
and dual 10-bit transmit DACs while providing the high-
est dynamic performance at ultra-low power. The ADCs’
analog I-Q input amplifiers are fully differential and
accept 1V
P-P
full-scale signals. Typical I-Q channel
phase matching is
±0.2°
and amplitude matching is
±0.05dB.
The ADCs feature 48.4dB SINAD and 70dBc
spurious-free dynamic range (SFDR) at f
IN
= 5.5MHz and
f
CLK
= 40MHz. The DACs’ analog I-Q outputs are fully
differential with
±400mV
full-scale output, and 1.4V com-
mon-mode level. Typical I-Q channel phase matching is
±0.15°
and gain matching is
±0.05dB.
The DACs also
feature dual 10-bit resolution with 72dBc SFDR, and
57dB SNR at f
OUT
= 2.2MHz and f
CLK
= 40MHz.
The ADCs and DACs operate simultaneously or indepen-
dently for frequency-division duplex (FDD) and time-divi-
sion duplex (TDD) modes. A 3-wire serial interface
controls power-down and transceiver modes of opera-
tion. The typical operating power is 75.6mW at f
CLK
=
40Msps with the ADCs and DACs operating simultane-
ously in transceiver mode. The MAX5865 features an
internal 1.024V voltage reference that is stable over the
entire operating power-supply range and temperature
range. The MAX5865 operates on a +2.7V to +3.3V ana-
log power supply and a +1.8V to +3.3V digital I/O power
supply for logic compatibility. The quiescent current is
8.5mA in idle mode and 1µA in shutdown mode. The
MAX5865 is specified for the extended (-40°C to +85°C)
temperature range and is available in a 48-pin thin QFN
package.
Functional Diagram
IA+
IA-
QA+
QA-
ADC
ADC
OUTPUT
MUX
ADC
DA0–DA7
Applications
Narrowband/Wideband CDMA Handsets
and PDAs
Fixed/Mobile Broadband Wireless Modems
3G Wireless Terminals
CLK
ID+
ID-
QD+
QD-
REFP
COM
REFN
REFIN
REF AND
BIAS
DAC
DAC
INPUT
MUX
DAC
DD0–DD9
Ordering Information
PART
MAX5865ETM
MAX5865E/D
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
48 Thin QFN-EP*
(7mm x 7mm)
Dice**
SERIAL
INTERFACE
AND SYSTEM
CONTROL
DIN
SCLK
CS
*EP
= Exposed paddle.
**Contact
factory for dice specifications.
Pin Configuration appears at end of data sheet.
MAX5865
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
MAX5865
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND, OV
DD
to OGND................................-0.3V to +3.3V
GND to OGND.......................................................-0.3V to +0.3V
IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN,
REFIN, COM to GND ..............................-0.3V to (V
DD
+ 0.3V)
DD0–DD9, SCLK, DIN,
CS,
CLK,
DA0–DA7 to OGND .............................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin Thin QFN (derate 26.3mW/°C above
+70°C)..............................................................................2.1W
Thermal Resistance
θ
JA
.................................................+38°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
REFP
= C
REFN
= C
COM
= 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
V
DD
OV
DD
ADC operating mode, f
IN
= 5.5MHz, f
CLK
=
40MHz, DAC operating mode, f
OUT
= 2.2MHz
ADC operating mode (Rx), f
IN
= 5.5MHz,
f
CLK
= 40MHz, DAC digital inputs at zero or
OV
DD
V
DD
Supply Current
DAC operating mode (Tx), f
OUT
= 2.2MHz,
f
CLK
= 40MHz, ADC off
Standby mode, DAC digital inputs and CLK
at zero or OV
DD
Idle mode, DAC digital inputs at zero or
OV
DD
, f
CLK
= 40MHz
Shutdown mode, digital inputs and CLK at
zero or OV
DD
,
CS
= OV
DD
ADC operating mode, f
IN
= 5.5MHz, f
CLK
=
40Msps, DAC operating mode, f
OUT
=
2.2MHz
OV
DD
Supply Current
Idle mode, DAC digital inputs at zero or
OV
DD,
f
CLK
= 40MHz
Shutdown mode, DAC digital inputs and
CLK at zero or OV
DD
,
CS
= OV
DD
1
2.7
1.8
25.2
3.0
3.3
V
DD
32
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
21
mA
12.8
2.0
11
µA
3.8
mA
37.4
µA
1
2
_______________________________________________________________________________________
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
REFP
= C
REFN
= C
COM
= 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
ADC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
DC Gain Matching
Offset Matching
Gain Temperature Coefficient
Power-Supply Rejection
ADC ANALOG INPUT
Input Differential Range
Input Common-Mode Voltage
Range
Input Impedance
ADC CONVERSION RATE
Maximum Clock Frequency
Data Latency
ADC DYNAMIC CHARACTERISTICS
(Note 3)
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
Ratio
Spurious-Free Dynamic Range
Third-Harmonic Distortion
Intermodulation Distortion
Third-Order Intermodulation
Distortion
Total Harmonic Distortion
SNR
SINAD
SFDR
HD3
IMD
IM3
THD
f
IN
= 5.5MHz
f
IN
= 20MHz
f
IN
= 5.5MHz
f
IN
= 20MHz
f
IN
= 5.5MHz
f
IN
= 20MHz
f
IN
= 5.5MHz
f
IN
= 20MHz
f
1
= 2MHz, -7dBFS; f
2
= 2.01MHz, -7dBFS
f
1
= 2MHz, -7dBFS; f
2
= 2.01MHz, -7dBFS
f
IN
= 5.5MHz
f
IN
= 20MHz
58
46.5
47
48.5
48.2
48.4
48.2
70
70
-75.4
-75
-66
-70
-71
-70
-57
dB
dB
dBc
dBc
dBc
dBc
dBc
f
CLK
(Note 2)
Channel I
Channel Q
5
5.5
40
MHz
Clock
cycles
R
IN
C
IN
Switched capacitor load
V
ID
Differential or single-ended inputs
±0.512
V
DD
/ 2
120
5
V
V
kΩ
pF
PSRR
Offset error (V
DD
±5%)
Gain error (V
DD
±5%)
INL
DNL
No missing codes over temperature
Residual DC offset error
Includes reference error
8
±0.15
±0.15
±0.22
±0.48
±0.03
±3
±42
±0.2
±0.07
±5
±5
±0.25
Bits
LSB
LSB
%FS
%FS
dB
LSB
ppm/°C
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX5865
_______________________________________________________________________________________
3
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
MAX5865
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
REFP
= C
REFN
= C
COM
= 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at T
A
= +25°C, unless otherwise noted.) (Note 1)
Large-Signal Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
ADC INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
Amplitude Matching
Phase Matching
DAC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
DAC DYNAMIC PERFORMANCE
DAC Conversion Rate
Noise over Nyquist
Output-of-Band Noise Power
Density
Glitch Impulse
Spurious-Free Dynamic Range
Total Harmonic Distortion
(to Nyquist)
Signal-to-Noise Ratio
(to Nyquist)
DAC-to-DAC Output Isolation
Gain Mismatch Between DAC
Outputs
Phase Mismatch Between DAC
Outputs
SFDR
THD
SNR
f
CLK
= 40MHz
f
CLK
= 22MHz
f
OUT
= 2.2MHz
f
OUT
= 200kHz
59
N
D
N
O
(Note 2)
f
OUT
= 2.2MHz, f
CLK
= 40MHz
f
OUT
= 1.2MHz, f
CLK
= 22MHz,
offset = 10MHz
-130.6
-130.9
10
72.3
73.5
-70
57
-58.5
40
Msps
dBc/Hz
dBc/Hz
pVs
dBc
dB
dB
N
INL
DNL
Guaranteed monotonic
Residual DC offset
Include reference error
-35
10
±1
±0.5
±3
+35
Bits
LSB
LSB
LSB
LSB
f
INX
= 5.5MHz at -0.5dBFS, f
INY
= 0.3MHz at
-0.5dBFS (Note 5)
f
IN
= 5.5MHz at -0.5dBFS (Note 6)
f
IN
= 5.5MHz at -0.5dBFS (Note 6)
-75
±0.05
±0.2
dB
dB
Degrees
1.5
×
full-scale input
FBW
A
IN
= -0.5dBFS
440
3.3
2.7
2
MHz
ns
ps
RMS
ns
f
CLK
= 40MHz, f
OUT
= 2.2MHz
f
CLK
= 40MHz, f
OUT
= 2.2MHz
DAC INTERCHANNEL CHARACTERISTICS
f
OUTX, Y
= 2.2MHz, f
OUTX, Y
= 2.0MHz
f
OUT
= 2.2MHz, f
CLK
= 40MHz
f
OUT
= 2.2MHz, f
CLK
= 40MHz
80
0.05
±0.15
dB
dB
Degrees
4
_______________________________________________________________________________________
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, C
REFP
= C
REFN
= C
COM
= 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
DAC ANALOG OUTPUT
Full-Scale Output Voltage
Output Common-Mode Range
ADC-DAC INTERCHANNEL CHARACTERISTICS
ADC-DAC Isolation
ADC-DAC TIMING CHARACTERISTICS
CLK Rise to I-ADC Channel-I
Output Data Valid
CLK Fall to Q-ADC Channel-Q
Output Data Valid
I-DAC Data to CLK Fall Setup
Time
Q-DAC Data to CLK Rise Setup
Time
CLK Fall to I-DAC Data Hold Time
CLK Rise to Q-DAC Data Hold Time
Clock Duty Cycle
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
Falling Edge of
CS
to Rising Edge
of First SCLK Time
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Period
SCLK to
CS
Setup Time
CS
High Pulse Width
20% to 80%
SERIAL INTERFACE TIMING CHARACTERISTICS
t
CSS
t
DS
t
DH
t
CH
t
CL
t
CP
t
CS
t
CSW
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
Figure 5 (Note 4)
From shutdown to Rx mode, Figure 6, ADC
settles to within 1dB
Shutdown Wake-Up Time
t
WAKE,SD
From shutdown to Tx mode, Figure 6, DAC
settles to within 10 LSB error
10
10
0
25
25
50
0
80
ns
ns
ns
ns
ns
ns
ns
ns
t
DOI
t
DOQ
t
DSI
t
DSQ
t
DHI
t
DHQ
Figure 3 (Note 4)
Figure 3 (Note 4)
Figure 4 (Note 4)
Figure 4 (Note 4)
Figure 4 (Note 4)
Figure 4 (Note 4)
10
10
0
0
50
±15
2.6
7.4
6.9
9
9
ns
ns
ns
ns
ns
ns
%
%
ns
ADC f
INI
= f
INQ
= 5.5MHz, DAC f
OUTI
=
f
OUTQ
= 2.2MHz, f
CLK
= 40MHz
75
dB
V
FS
1.29
±400
1. 5
mV
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX5865
MODE RECOVERY TIMING CHARACTERISTICS
20
µs
40
_______________________________________________________________________________________
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
