8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
8Mb
ZBT
®
SRAM
WITH S
MART
ZBT™ OPTION
FEATURES
• S
MART
ZBT
™
adapts to system timing to minimize
potential bus contention
• High frequency and 100 percent bus utilization
• Fast cycle times: 6ns, 7.5ns and 10ns
• Single +3.3V
±5%
power supply (V
DD
)
• Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
• Advanced control logic for minimum control
signal interface
• Individual BYTE WRITE controls may be tied LOW
• Single R/W# (read/write) control pin
• CKE# pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to
eliminate the need to control OE#
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or Interleaved Burst Modes
• Burst feature (optional)
• Pin/function compatibility with 2Mb, 4Mb, and
16Mb ZBT SRAM
• Automatic power-down
MT55L512L18P, MT55L512V18P,
MT55L256L32P, MT55L256V32P,
MT55L256L36P, MT55L256V36P
3.3V V
DD
, 3.3V or 2.5V I/O
100-PIN TQFP*
119-PIN BGA
OPTIONS
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
512K x 18
256K x 32
256K x 36
2.5V I/O
512K x 18
256K x 32
256K x 36
• S
MART
ZBT option
• Package
100-pin TQFP
119-pin, 14mm x 22mm BGA
*S
MART
ZBT option available.
Part Number Example:
MARKING
-6
-7.5*
-10*
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-STANDARD MS-028 BHA (PBGA).
GENERAL DESCRIPTION
The Micron
®
Zero Bus Turnaround
™
(ZBT
®
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
The S
MART
ZBT feature enhances the ability of the
SRAM to run in systems with minimal transition time
on the data bus, whether using multiple SRAMs or
complementing ASIC designs.
Micron’s S
MART
ZBT feature allows the
t
KHQX1 (clock
HIGH to output valid) to adapt to the system clock, thus
reducing contention issues. The S
MART
ZBT will drive
the bus turn-on later than the traditional ZBT.
Micron’s 8Mb ZBT SRAMs integrate a 512K x 18,
256K x 32, or 256K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
MT55L512L18P
MT55L256L32P
MT55L256L36P
MT55L512V18P
MT55L256V32P
MT55L256V36P
Z
T
B
MT55L256L32PT-7.5
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P.p65 – Rev. 3/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
GENERAL DESCRIPTION (continued)
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#), and
read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK), and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW, or left
unconnected if burst is unused. The data-out (Q), en-
abled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes wide as
controlled by the write control inputs.
All READ, WRITE, and DESELECT cycles are initi-
ated by the ADV/LD# input. Subsequent burst ad-
dresses can be internally generated as controlled by the
burst advance pin (ADV/LD#). Use of burst mode is
optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The data associated with the address is
required two cycles later, or on the rising edge of clock
cycle three.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa#
controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; and BWd# controls DQd pins. Cycle
types can only be defined when an address is loaded,
i.e., when ADV/LD# is LOW. Parity/ECC bits are only
available on the x36 version.
Micron’s 8Mb ZBT SRAMs operate from a +3.3V V
DD
power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requir-
ing high bandwidth and zero bus turnaround delays.
Please refer to Micron’s Web site (www.micron.com/
mti/msp/html/sramprod.html)
for the latest data sheet.
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P.p65 – Rev. 3/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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