Advanced v.1
HiRel
SX-A Family FPGAs
Le a di n g E d ge P er f o r m a n ce
• 100% Military Temperature Tested (–55°C to +125°C)
• 66 MHz PCI Compliant
• CPLD and FPGA Integration
• Single-Chip Solution
• Configurable I/O Support for 3.3V/5.0V PCI, LVTTL,
and TTL
• Configurable Weak Resistor Pull-up or Pull-down for
Tristated Outputs at Power Up
• 100% Resource Utilization with 100% Pin Locking
• 2.5V, 3.3V, and 5.0V Mixed-Voltage Operation with 5.0V
Input Tolerance and 5.0V Drive Strength
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
• Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• 215 MHz System Performance (Military Temperature)
• 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
• 284 MHz Internal Performance (Military Temperature)
Sp e ci f i c a t i on s
• 12,000 to 108,000 Available System Gates
• Up to 225 User-Programmable I/O Pins
• Up to 2,012 Dedicated Flip-Flops
• 0.25
µ
CMOS Process Technology
Fe a t ur es
• I/Os with Live or “Hot-Swapping” Capability
• Power Up/Down Friendly (No Sequencing Required for
Supply Voltages)
• Offered as Commercial or Military Temperature Tested
and Class B
• Cost Effective QML MIL-Temp Plastic Packaging Options
• Standard Hermetic Package Offerings
• QML Certified Devices
Pr od uc t P r o f i l e
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Global Clocks
Quadrant Clocks
Boundary Scan Testing
3.3V/5.0V PCI
Clock-to-Out
Input Setup (External)
Speed Grades
Package
(by pin count)
CQFP
A54SX32A
32,000
48,000
2,880
1,800
1,080
225
3
0
Yes
Yes
5.4 ns
0 ns
Std, –1
208, 256
A54SX72A
72,000
108,00
6,036
4,024
2,012
206
3
4
Yes
Yes
6.7 ns
0 ns
Std, –1
208, 256
April 2000
1
© 2000 Actel Corporation
G en er al D e sc r i p t i on
Q M L Ce r t i f i c a t i o n
Actel’s SX-A family of FPGAs features a sea-of-modules
architecture that delivers device performance and
integration levels not currently achieved by any other FPGA
architecture. SX-A devices greatly simplify design time,
enable dramatic reductions in design costs and power
consumption, and further decrease time to market for
performance-intensive applications.
Actel’s SX-A architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient mapping
of synthesized logic functions. The routing and interconnect
resources are in the metal layers above the logic modules,
providing optimal use of silicon. This enables the entire
floor of the device to be spanned with an uninterrupted grid
of fine-grained, synthesis-friendly logic modules (or
“sea-of-modules”), which reduces the distance signals have
to travel between logic modules. To minimize signal
propagation delay, SX-A devices employ both local and
general routing resources. The high-speed local routing
resources (DirectConnect and FastConnect) enable very
fast local signal propagation that is optimal for fast
counters, state machines, and datapath logic. The general
system of segmented routing tracks allows any logic module
in the array to be connected to any other logic or I/O
module. Within this system, propagation delay is minimized
by limiting the number of antifuse interconnect elements to
five (90 percent of connections typically use only three
antifuses). The unique local and general routing structure
featured in SX-A devices gives fast and predictable
performance, allows 100 percent pin locking with full logic
utilization, enables concurrent PCB development, reduces
design time, and allows designers to achieve performance
goals with minimum effort.
Further complementing SX-A’s flexible routing structure is a
hardwired, constantly loaded clock network that has been
tuned to provide fast clock propagation with minimal clock
skew. Additionally, the high performance of the internal
logic has eliminated the need to embed latches or flip-flops
in the I/O cells to achieve fast clock-to-out or fast input
setup times. SX-A devices have easy-to-use I/O cells that do
not require HDL instantiation, facilitating design re-use and
reducing design and verification time.
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense for monolithic integrated circuits. QML
certification is a good example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military, and space applications.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows
for a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
D ev e l op m en t T o ol S up p or t
The SX-A devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place-and-route tools.
Designer Advantage, Actel’s suite of FPGA development
point tools for PCs and Workstations, includes the ACTgen
Macro Builder, Designer with DirectTime timing-driven
place-and-route and analysis tools, and device programming
software.
In addition, the SX-A devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100-percent real-time observation and analysis of a
device's internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer II, an easy to
use integrated verification and logic analysis tool that can
sample data at 100 MHz (asynchronous) or 66 MHz
(synchronous). Silicon Explorer II attaches to a PC’s
standard COM port, turning the PC into a fully functional
18-channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several hours
per cycle to only a few seconds.
2
Hi R e l S X -A F a m i ly F PG A s
O r d e r i n g I nf o r m a t i o n
A54SX16
A
–
1
CQ
208
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
M = Military (–55 to +125°C)
PP = Pre-production
B = MIL-STD-883
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
A = 0.25µ CMOS Technology
Part Number
A54SX32 = 48,000 System Gates
A54SX72 = 108,000 System Gates
Pr od uc t P l a n
Speed Grade*
Std
A54SX32A Device
208-Pin Ceramic Quad Flat Pack (CQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
A54SX72A Device
208-Pin Ceramic Quad Flat Pack (CQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
–1
C
Application
M
•
B
Contact your Actel sales representative for product availability.
Applications: C = Commercial
Availability: P = Planned
M = Military
B = MIL-STD-883
*Speed Grade: –1 = Approx. 15% faster than Standard
•
Only Std and –1 Speed Grades
C er a m i c De v i ce R es ou r c es
User I/Os (including clock buffers)
Device
A54SX32A
A54SX72A
CQFP
208-Pin
174
171
CQFP
256-Pin
228
213
Contact your Actel sales representative for product availability.
Package Definitions
CQFP = Ceramic Quad Flat Pack
3
A ct e l M I L - ST D - 88 3 Pr od uc t F l ow
Step
1.
2.
3.
4.
Screen
Internal Visual
Temperature Cycling
Constant Acceleration
Seal
a. Fine
b. Gross
Visual Inspection
Pre-Burn-In
Electrical Parameters
Burn-in Test
Interim (Post-Burn-In)
Electrical Parameters
Percent Defective Allowable
Final Electrical Test
a. Static Tests
(1) 25°C
(Subgroup 1, Table I)
(2) –55°C and +125°C
(Subgroups 2, 3, Table I)
b. Functional Tests
(1) 25°C
(Subgroup 7, Table I)
(2) –55°C and +125°C
(Subgroups 8A and 8B, Table I)
c. Switching Tests at 25°C
(Subgroup 9, Table I)
11.
Note:
External Visual
883 Method
2010, Test Condition B
1010, Test Condition C
2001, Test Condition D or E,
Y
1
, Orientation Only
1014
100%
100%
2009
In accordance with applicable Actel
device specification
1015, Condition D,
160 hours @ 125°C or 80 hours @ 150°C
In accordance with applicable Actel
device specification
5%
In accordance with applicable Actel
device specification, which includes a, b, and c:
100%
5005
5005
100%
5005
5005
100%
5005
2009
100%
100%
100%
100%
100%
All Lots
883—Class B
Requirement
100%
100%
100%
5.
6.
7.
8.
9.
10.
When Destructive Physical Analysis (DPA) is performed on Class B devices, the step coverage requirement as specified in Method 2018
must be waived.
4
Hi R e l S X -A F a m i ly F PG A s
SX - A F am i l y A r ch i t e ct ur e
The SX-A family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
P rog ra m ma ble Int er con nect E l em ent
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives the SX-A family abundant routing resources and
provides excellent protection against design pirating.
Reverse engineering is virtually impossible because it is
extremely difficult to distinguish between programmed and
unprogrammed antifuses, and there is no configuration
bitstream to intercept.
Additionally, the interconnect (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
The SX-A family provides efficient use of silicon by locating
the routing interconnect resources between the Metal 2
(M2) and Metal 3 (M3) layers (Figure
1).
This completely
eliminates the channels of routing and interconnect
resources between logic modules (as implemented on
SRAM FPGAs and previous generations of antifuse FPGAs),
and enables the entire floor of the device to be spanned
with an uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
Routing Tracks
Metal 3
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
Metal 2
Metal 1
Tungsten Plug
Contact
Silicon Substrate
Note:
A54SX72A has 4 layers of metal with the antifuse between Metal 3 and Metal 4.
Figure 1 •
SX-A Family Interconnect Elements
5
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