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NCP5201
Dual Output
DDR Power Controller
The NCP5201 Dual DDR Power Controller is specifically
designed as a total power solution for a high current DDR memory
system. This IC combines the efficiency of a PWM controller for the
VDDQ supply with the simplicity of a linear regulator for the VTT
memory termination voltage. The secondary regulator (VTT) is
designed to automatically track at half the primary regulator voltage
(VDDQ). An internal power good voltage monitor tracks both
VDDQ and VTT outputs and notifies the user in the event of a fault
on either output. Protective features include soft−start circuitry and
undervoltage monitoring of VCC and VSTBY. The IC is packaged in
a 5
×
6 QFN−18.
Features
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MARKING
DIAGRAM
1
1
NCP5201
AWLYYWW
G
G
•
•
•
•
•
•
•
•
•
•
•
•
Incorporates VDDQ, VTT Regulators
Internal Switching Standby Regulator for VDDQ
All External Power MOSFETs Are N−Channel
Adjustable VDDQ
VTT Tracks VDDQ/2
Fixed Switching Frequency of 250 kHz for VDDQ in Normal Mode
Doubled Switching Frequency (500 kHz) for Standby Mode
Soft−Start Protection for VDDQ
Undervoltage Monitor
Short−Circuit Protection for Both VDDQ and VTT Outputs
Housed in a space saving 5
×
6 QFN−18
Pb−Free Packages are Available*
18−LEAD QFN, 5 x 6 mm
MN SUFFIX
CASE 505
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Typical Applications
•
DDR Termination Voltage
•
Active Termination Busses (SSTL−2, SSTL−3)
FBDDQ
FBVTT
PGND
VSTBY
VTT
VTT
OCDDQ
VDDQ
NC
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
SS
COMP
VCC
TGDDQ
BGDDQ
SDDQ
AGND
S3_EN
PWRGD
NOTE:
Pin 19 is the thermal pad on the bottom of
the device.
ORDERING INFORMATION
Device
NCP5201MN
NCP5201MNG
NCP5201MNR2
NCP5201MNR2G
Package
18−Lead QFN
18−Lead QFN
(Pb−Free)
Shipping
†
61 Units / Rail
61 Units / Rail
18−Lead QFN 2500/T
ape & Reel
18−Lead QFN 2500/T
ape & Reel
(Pb−Free)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCP5201/D
1
April, 2006 − Rev. 11
NCP5201
5V
L1 1.0
mH
R2
10 k
R3
10 k
C1
1000
mF
5 VSTBY
C4
1.0
mF
12 V
C5
1.0
mF
C2
1.0
mF
AGND
S3
4
11
S3_EN
R6
16
W
C10
100 nF
R7
1.15 k
C11
6.8
nF
R12
20 k
8
VDDQ
1
C12
10 nF 17
18
C13
22 nF
12
7
C17
0.1
mF
AGND
RL1
62 k
FBDDQ
PWRGD
TGDDQ
SDDQ
BGDDQ
COMP
VTT
SS
AGND
OCDDQ
VTT
FBVTT
PGND
15
13
14
5
6
2
3
VSTBY
VCC
16
10
R8 4.7
W
S
NTD60N02R
D
D
NTD60N02R
S
L2 2.2
mH
NTD60N02R
COUT
VTT (1000
mF
x3)
VDDQ
R1 4.7
W
R5 4.7
W
+
R10
1.1 k
+
C14
1000
mF
+
C15
470
mF
C15
1.0
mF
Figure 1. Application Diagram
MAXIMUM RATINGS
Rating
Power Supply Voltage (Pin 4) to PGND (Pin 3) and GND (Pin 12)
Power Supply Voltage, VCC (Pin 16) to PGND (Pin 3) and GND (Pin 12)
Gate Drive Voltage (Pins 14, 15)
Input/Output Pins (Pins 1, 2, 5−11, 13, 17−18)
Package Thermal Resistance, Junction−to−Ambient
Operating Junction Temperature Range
Operating Ambient Temperature Range
Storage Temperature Range
Moisture Sensitivity Level
Symbol
VSTBY
VCC
Vg
V
IO
R
qJA
T
J
T
A
T
stg
MSL
Value
−0.3, 6.0
−0.3, 14
−0.3 DC,
−4.0 for < 1.0
ms;
14
−0.3, 6.0
35
0 to +150
0 to +70
−55 to +150
2
Unit
V
V
V
V
°C/W
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM)
≤
2.0 kV per JEDEC Standard JESD22−A114 except Pin 15 which is
≤
1.5 kV.
Machine Model (MM)
≤
200 V per JEDEC Standard JESD22−A115 except Pin 14 which is
≤
100 V.
2. Latchup Current Maximum Rating:
≤
150 mA per JEDEC Standard JESD78.
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2
NCP5201
ELECTRICAL CHARACTERISTICS
(VSTBY = 5.0 V, VCC = 12 V, T
A
= 0 to 70°C, L2 = 1.7
mH,
COUT = 3770
mF,
COUT2 = 220
mF,
RL1 = 100 kW, R7 = 1.0 kW, R10 = 1.0 k, R12 = 20 kW, R6 = 16
W,
C12 = 3.0 nF, C11 = 6.0 nF, C10 = 80 nF, for min/max values unless
otherwise noted)
Characteristic
SUPPLY CURRENT
S0 Mode Supply Current from VSTBY
S3 Mode Supply Current from VSTBY
S0 Mode Supply Current from VCC
IST_S0
IST_S3
ICC_S0
S3_EN = LOW, VCC = 12 V
S3_EN = HIGH, VCC = 0 V
EN = HIGH, VCC = 12 V,
2.0 nF Capacitive Load to TGDDQ
and BGDDQ
−
−
−
−
−
−
8.0
4.0
30
mA
mA
mA
Symbol
Test Conditions
Min
Typ
Max
Unit
UNDERVOLTAGE MONITOR
VSTBY UVLO Lower Threshold
Ratio of VSTBY UVLO Upper to
Lower Threshold
VCC UV Monitor Lower Threshold
Ratio of VCC UV Monitor Upper to
Lower Threshold
VDDQ SWITCHING REGULATOR
FBDDQ Feedback Voltage,
Control Loop in Regulation
Feedback Input Current
Oscillator Frequency in S0 Mode
OCDDQ Pin Current Sink
Minimum Duty Cycle
Maximum Duty Cycle
Soft−Start Timing
VDDQ STANDBY REGULATOR
FBDDQ Feedback Voltage, Control
Loop in Regulation
Load Regulation
Peak Current Limit
Peak Current Limit Blanking Time
Oscillator Frequency in S3 Mode
VDDQ ERROR AMPLIFIER
DC Gain
Unity Gain Bandwidth
Slew Rate
VTT ACTIVE TERMINATOR
VTT Tracking VDDQ/2 at S0 Mode
dVTT0
VDDQ/2 − VTT,
IOUT = 1.8 A (Sink Current)
IOUT = −1.8 A (Source Current)
−
−
−30
−
−
−
−
−
−2.3
2.3
−
30
−
−
mV
mV
A
A
GAIN
Ft
SR
−
COMP_GND = 200 nF, 1.0
W
in
series (Test circuit only)
COMP_GND = 10 pF
−
−
−
70
2.0
8.0
−
−
−
dB
MHz
V/ms
VFBQ
LOADreg
ILIMstbpk
tbk
Fstb
T
A
= 25°C
T
A
= 0 to 70°C
ILOAD from 50 mA to 650 mA
−
−
−
1.281
1.274
−
−
400
−
1.300
−
0.4
2.0
−
500
1.319
1.326
−
−
−
−
V
V
%
A
ns
kHz
VFBQ
Ifb
F
IOC
Dmin
Dmax
tss1
T
A
= 25°C
T
A
= 0 to 70°C
V(FBDDQ) = 1.3 V
−
V(OCDDQ) = 4.0 V
−
−
C
SS
= 33 nF
1.271
1.264
−
225
6.0
0
−
10
1.300
−
−
250
10
−
−
16
1.326
1.333
0.5
275
14
−
100
−
V
V
mA
kHz
mA
%
%
ms
VSBUV−
VSBUV+/
VSBUV−
VCCUV−
VCCUV+/
VCCUV−
−
−
−
−
−
−
−
−
4.25
1.05
9.23
1.14
−
−
−
−
V
−
V
−
Source Current Limit
Sink Current Limit
ILIMVTsrc
ILIMVTsnk
3. Guaranteed by design, not tested in production.
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3
NCP5201
ELECTRICAL CHARACTERISTICS
(VSTBY = 5.0 V, VCC = 12 V, T
A
= 0 to 70°C, L2 = 1.7
mH,
COUT = 3770
mF,
COUT2 = 220
mF,
RL1 = 100 kW, R7 = 1.0 kW, R10 = 1.0 k, R12 = 20 kW, R6 = 16
W,
C12 = 3.0 nF, C11 = 6.0 nF, C10 = 80 nF, for min/max values unless
otherwise noted)
Characteristic
CONTROL SECTION
S3_EN Pin Threshold HIGH
S3_EN Pin Threshold LOW
S3_EN Pin Input Current
PWRGD Pin ON Resistance
PWRGD Pin OFF Current
PWRGD LOW−to−HIGH Hold Time,
For S3 to S0 or S5 to S0
GATE DRIVERS
TGDDQ Gate Pull−HIGH Resistance
VCC = 12 V,
V(TGDDQ) = 11
V
VCC = 12 V,
V(TGDDQ) = 1.0
V
VCC = 12 V,
V(BGDDQ) = 11
V
VCC = 12 V,
V(BGDDQ) = 1.0
V
RH_TG
−
3.0
−
W
−
−
−
−
−
−
S3_EN_H
S3_EN_L
IIN_EN
PWRGD_R
PWRGD_
LEAK
thold
1.4
−
−
−
−
−
−
−
−
−
−
−
−
0.5
0.5
80
1.0
200
V
V
mA
W
mA
ms
Symbol
Test Conditions
Min
Typ
Max
Unit
TGDDQ Gate Pull−LOW Resistance
RL_TG
−
2.5
−
W
BGDDQ Gate Pull−HIGH Resistance
RH_BG
−
3.0
−
W
BGDDQ Gate Pull−LOW Resistance
RL_BG
−
1.3
−
W
PIN DESCRIPTION
Pin No.
1
2
3
4
Symbol
FBDDQ
FBVTT
PGND
Description
VDDQ feedback pin for closed loop regulation.
VTT regulator sense voltage.
Power ground.
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Ñ
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ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
Ñ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
Ñ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
Ñ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
Ñ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
Ñ
ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
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ÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑÑ
ÑÑÑÑÑÑÑÑÑÑÑ
VSTBY
VTT
5 V Standby input voltage.
VTT regulator output.
5, 6
7
8
9
OCDDQ
VDDQ
NC
Overcurrent sense and program input for the VDDQ high−side FET.
Reference input and power stage input for VTT regulator.
Not connected.
10
11
PWRGD
S3_EN
AGND
Open drain status output. High impedance when the product is operating in S0 state and both
DDQ and VTT regulators are in compliance.
S3 mode enable input. High to enable.
12
13
14
15
16
17
18
19
Analog ground connection and remote ground sense.
Inductor driven node and current limit sense input.
SDDQ
BGDDQ
TGDDQ
VCC
Gate driver output, VDDQ Low−Side N−Channel Power FET. Active during S0 mode.
Gate driver output, VDDQ High−Side N−Channel Power FET. Active during S0 mode.
12 Volt input supply. This voltage is monitored by power good circuitry for mode selection.
VDDQ error amplifier compensation node.
Soft−start capacitor connection to ground.
COMP
SS
TH_PAD
Copper pad on bottom of IC used for heatsinking. This pin should be connected to the ground
plane under the IC.
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