April 2008
HYS72T128901EFA–3S
HYS72T256[8/9]21EFA–[25F/3S]
HYS72T512[8/9][2/4]0EFA–[25F/3S]
240-Pin Fully-Buffered DDR2 SDRAM Modules
DDR2 SDRAM
RoHS Compliant Products
Advance
Internet Data Sheet
Rev.0.75
Advance Internet Data Sheet
HYS72T[128/256/512][8/9][0/2/4][0/1]EFA–[25F/3S]
Fully-Buffered DDR2 SDRAM Modules
Revision History: Rev.0.75, 2008-04-23
All
All
All
All
Adapted Internet Version
Portfolio change
Portfolio change
Initial document
Previous Revision: Rev. 0.60, 2008-03-11
Previous Revision: Rev. 0.50, 2008-01
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_A4, 4.20, 2008-01-25
02292008-9O2H-NG6P
2
Advance Internet Data Sheet
HYS72T[128/256/512][8/9][0/2/4][0/1]EFA–[25F/3S]
Fully-Buffered DDR2 SDRAM Modules
1
1.1
Overview
Features
• Detects errors on the channel and reports them to the host
memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Automatic Channel Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• Hot Add-on and Hot Remove Capability.
• MBIST and IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Low profile: 133.35 mm x 30.35 mm
• 240 Pin gold plated card connector with 1.00mm contact
centers (standard pending).
• Based on industry standard reference card designs
(standard pending).
• SPD (Serial Presence Detect) with 256 Byte serial
E
2
PROM.Performance.
• RoHS Compliant Products
1)
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
• 240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM
Module for PC, Workstation and Server main memory
applications.
• One rank 128M
×
72 , two rank 256M
×
72, 512M
×
72 and
four rank 512M
×
72 module organization, and 128M
×
8,
256M
×
4 chip organization.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
• 4GB, 2GB, 1GB Modules built with chipsize packages PG-
TFBGA-60.
• Re-drive and re-sync of all address, command, clock and
data signals using AMB (Advanced Memory Buffer).
• High-Speed Differential Point-to-Point Link Interface at 1.5
V (standard pending).
• Host Interface and AMB component industry standard
compliant.
• Supports SMBus protocol interface for access to the AMB
configuration registers.
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL5
CL4
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–25F
DDR2–800D
PC2–6400D
5–5–5
–3S
DDR2–667D
PC2–5300D
5–5–5
200
333
266
15
15
45
60
Unit
t
CK
MHz
MHz
MHz
ns
ns
ns
ns
f
CK3
f
CK5
f
CK4
t
RCD
t
RP
t
RAS
t
RC
200
400
266
12.5
12.5
45
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev.0.75, 2008-04-23
02292008-9O2H-NG6P
3
Advance Internet Data Sheet
HYS72T[128/256/512][8/9][0/2/4][0/1]EFA–[25F/3S]
Fully-Buffered DDR2 SDRAM Modules
1.2
Description
AMB communicates with the host controller and / or the
adjacent DIMMs on a system board using an Industry
Standard High-Speed Differential Point-to-Point Link
Interface at 1.5 V.
The Advanced Memory Buffer also allows buffering of
memory traffic to support large memory capacities. All
memory control for the DRAM resides in the host, including
memory request initiation, timing, refresh, scrubbing, sparing,
configuration access, and power management. The
Advanced Memory Buffer interface is responsible for handling
channel and memory requests to and from the local DIMM
and for forwarding requests to other DIMMs on the memory
channel. Fully Buffered DIMM provides a high memory
bandwidth, large capacity channel solution that has a narrow
host interface. The maximum memory capacity is 288 DDR2
SDRAM devices per channel or 8 DIMMs.
This document describes the electrical and mechanical
features of a 240-pin, PC2-5300F and PC2-6400F ECC type,
Fully Buffered Double-Data-Rate Two Synchronous DRAM
Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).
Fully Buffered DIMMs use commodity DRAMs isolated from
the memory channel behind a buffer on the DIMM. They are
intended for use as main memory when installed in systems
such as servers and workstations. PC2-5300F and refers to
the DIMM naming convention indicating the DDR2 SDRAMs
running at 333 respectively 400 MHz clock speed and offering
5300 resp. 6400 Mb/s peak bandwidth. FB-DIMM features a
novel architecture including the Advanced Memory Buffer.
This single chip component, located in the center of each
DIMM, acts as a repeater and buffer for all signals and
commands which are exchanged between the host controller
and the DDR2 SDRAMs including data in- and output. The
Rev.0.75, 2008-04-23
02292008-9O2H-NG6P
4
Advance Internet Data Sheet
HYS72T[128/256/512][8/9][0/2/4][0/1]EFA–[25F/3S]
Fully-Buffered DDR2 SDRAM Modules
TABLE 2
Ordering Information
Product Type
1)
PC2-6400 (5-5-5)
HYS72T512840EFA-25F
HYS72T512920EFA-25F
HYS72T512820EFA-25F
HYS72T256821EFA-25F
HYS72T256921EFA-25F
PC2-5300 (5-5-5)
HYS72T512840EFA-3S
HYS72T256921EFA-3S
HYS72T128901EFA-3S
4GB 4R×8 PC2–5300F–555–11–W0
2GB 2R×8 PC2–5300F–555–11–B0
1GB 1R×8 PC2–5300F–555–11–A0
4 Ranks, ECC
2 Ranks, ECC
1 Rank, ECC
1Gbit (×8)
1Gbit (×8)
1Gbit (×8)
4GB 4R×8 PC2–6400F–555–11–W0
4GB 2R×4 PC2–6400F–555–11–AB0
4GB 2R×4 PC2–6400F–555–11–AB0
2GB 2R×8 PC2–6400F–555–11–R0
2GB 2R×8 PC2–6400F–555–11–R0
4 Ranks, ECC
2 Ranks, ECC
2 Ranks, ECC
2 Ranks, ECC
2 Ranks, ECC
1Gbit (×8)
1Gbit (×4)
1Gbit (×4)
1Gbit (×8)
1Gbit (×8)
Compliance Code
2)
Description
SDRAM Technology
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400F–555–11–R0" where 6400F
means Fully-Buffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555–11" means Column Address Strobe (CAS) latency
=5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the Industry Standard SPD Revision 1.1 and
produced on the Raw Card "R".
TABLE 3
Address Format
DIMM
Density
4GB
4GB
2GB
2GB
1GB
Module
Organization
512M
×
72
512M
×
72
256M
×
72
256M
×
72
128M
×
72
Memory
Ranks
4
2
2
2
1
ECC/
Non-ECC
ECC
ECC
ECC
ECC
ECC
# of SDRAMs # of row/bank/column
bits
36
36
18
18
9
14/3/10
14/3/11
14/3/10
14/3/10
14/3/10
Raw
Card
W
AB
R
B
A
Rev.0.75, 2008-04-23
02292008-9O2H-NG6P
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
