(Preliminary)
Low Skew Zero Delay Buffer
FEATURES
Frequency Range 10MHz to 134 MHz
Output Options:
o
5 outputs
PL123-05
o
9 outputs
PL123-09
Zero input - output delay
Optional Drive Strength:
Standard (8mA)
PL123-05/-09
High (12mA)
PL123-05H/-09H
3.3V, ±10% operation
Available in Commercial and Industrial temperature
ranges
Available in 16-Pin SOP or TSSOP (PL123-09),
and 8-Pin SOP (PL123-05) packages
DESCRIPTION
The PL123-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123-05) or two (PL123-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123-09 allows control of the banks of
outputs by using the S1 and S2 inputs as shown in the
Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than
100ps,
the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
REF
PLL
Mux
CLKOUT
CLKA1
CLKA2
CLKA3
REF
CLKA2
CLKA1
GND
1
2
3
4
8
7
6
5
CLKOUT
CLKA4
VDD
CLKA3
REF
CLKA4
CLKB1
CLKA1
CLKA2
S1
S2
VDD
GND
CLKB1
CLKB3
CLKB4
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Selector
Inputs
(PL123-09 Only)
CLKB2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 4/9/08 Page 1
(Preliminary)
Low Skew Zero Delay Buffer
PIN DESCRIPTIONS
Name
REF
[1]
CLKA1
[2]
CLKA2
[2]
VDD
GND
CLKB1
[2]
CLKB2
[2]
S2
[3]
S1
[3]
CLKB3
[2]
CLKB4
[2]
CLKA3
[2]
CLKA4
[2]
CLKOUT
[2]
PL123-09
TSSOP-16L
1
2
3
4,13
5,12
6
7
8
9
10
11
14
15
16
SOP-16L
1
2
3
4,13
5,12
6
7
8
9
10
11
14
15
16
PL123-05
SOP-8L
1
3
2
6
4
-
-
-
-
-
-
5
7
8
Type
I
O
O
P
P
O
O
I
I
O
O
O
O
O
Description
Input reference frequency.
Buffered clock output, Bank A
Buffered clock output, Bank A
VDD connection
GND connection
Buffered clock output, Bank B
Buffered clock output, Bank B
Selector input
Selector input
Buffered clock output, Bank B
Buffered clock output, Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output. Internal feedback
on this pin.
Notes:
1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION FOR PL123-09
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
(Bank A)
Three-state
Driven
Driven
Driven
CLOCK B1–B4
(Bank B)
Three-state
Three-state
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
INPUT / OUTPUT SKEW CONTROL
The PL123-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally. Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact PhaseLink for more information.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 4/9/08 Page 2
(Preliminary)
Low Skew Zero Delay Buffer
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termi-
nation this will cause reflections ( looks like ringing ).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 4/9/08 Page 3
(Preliminary)
Low Skew Zero Delay Buffer
ABSOLUTE MAXIMUM CONDITIONS
Supply Voltage to Ground Potential ...... –0.5V to 4.6V
DC Input Voltage........................... V
SS
– 0.5V to 4.6V
Storage Temperature ........................–65°C to 150°C
OPERATING CONDITIONS
Parameter
Description
Min.
Max.
Unit
Junction Temperature………………………….. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)…………..> 2000V
V
DD
T
A
C
L
C
IN
t
PU
Supply Voltage
Commercial Operating Temperature (ambient temperature)
Industrial Operating Temperature (ambient temperature)
Load Capacitance, below 100 MHz
Load Capacitance, above 100 MHz
Input Capacitance
Power-up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic)
3.0
0
-40
―
―
―
0.05
3.6
70
85
30
10
7
250
V
C
C
pF
pF
pF
ms
ELECTRICAL CHARACTERISTICS
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
[4]
Output HIGH Voltage
[4]
Supply Current
(Unloaded Outputs)
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8 mA
I
OL
= 12 mA
I
OH
= –8 mA
I
OL
= –12 mA
66.67MHz with unloaded outputs
Commercial Temp.
66.67MHz with unloaded outputs
Industrial Temp.
–
2.5
–
–
–
2.4
–
–
0.8
–
50
100
0.4
–
32
45
V
V
µA
µA
V
V
mA
mA
Notes:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 4/9/08 Page 4
(Preliminary)
Low Skew Zero Delay Buffer
SWITCHING CHARACTERISTICS
Parameter Name
t
1
Output Frequency
Duty Cycle
[4]
= t2 ÷ t1
Duty Cycle
[4]
= t2 ÷ t1
t
3
t
4
t
5
t
6A
t
6B
t
7
t
8
t
J
t
LOCK
Rise Time
[4]
Rise Time
[4]
(High Drive)
Fall Time
[4]
Fall Time
[4]
(High Drive)
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge
[4]
Delay, REF Rising Edge to
CLKOUT Rising Edge
[4]
Device to Device Skew
[4]
Output Slew Rate
[4]
Cycle to Cycle Jitter
[4]
PLL Lock Time
[4]
[5]
Test Conditions
30-pF load
10-pF load
Measured at 1.4V, F
OUT
= 66.67MHz
Measured at 1.4V, F
OUT
<50MHz
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
Measured at VDD/2
Measured at VDD/2. Measured in PLL bypass
mode,
PL123-09 only.
Measured at VDD/2 on the CLKOUT pin
Measured between 0.8V and 2.0V using Test
Circuit #2
Measured at 66.67 MHz, loaded outputs
Stable power supply, valid clock presented on
REF pin
Min.
10
10
40
45
–
–
–
–
–
–
1
–
1
–
–
Typ.
–
–
50
50
2.5
1.5
2.5
1.5
–
0
5
0
–
75
–
Max.
100
134
60
55
–
–
–
–
250
±350
8.5
700
–
200
1
Unit
MHz
MHz
%
%
ns
ns
ns
ns
ps
ps
ns
ps
V/ns
ps
ms
Notes:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5. All parameters are specified with loaded outputs.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 4/9/08 Page 5
ADI 工业技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
