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NCP5351
4 A Synchronous Buck
Power MOSFET Driver
The NCP5351 is a dual MOSFET gate driver optimized to drive the
gates of both high−side and low−side Power MOSFETs in a
Synchronous Buck converter. The NCP5351 is an excellent
companion to multiphase controllers that do not have integrated gate
drivers, such as ON Semiconductor’s CS5323, CS5305 or CS5307.
This architecture provides a power supply designer the flexibility to
locate the gate drivers close to the MOSFETs.
The 4.0 A drive capability makes the NCP5351 ideal for minimizing
switching losses in MOSFETs with large input capacitance. Optimized
internal, adaptive nonoverlap circuitry further reduces switching
losses by preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate MOSFET drain
voltages as high as 25 V. Both gate outputs can be driven low, and
supply current reduced to less than 25
mA,
by applying a low logic
level to the Enable (EN) pin. An undervoltage lockout function
ensures that both driver outputs are low when the supply voltage is
low, and a thermal shutdown function provides the IC with
overtemperature protection.
The NCP5351 is pin−to−pin compatible with the SC1205 and is
available in a standard SO−8 package and thermally enhanced
DFN10.
Features
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MARKING
DIAGRAMS
8
8
1
SO−8
D SUFFIX
CASE 751
1
DFN10
MN SUFFIX
CASE 485C
A
L
Y
W
G
1
5351
ALYW
G
1
5351
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
4.0 A Peak Drive Current
Rise and Fall Times < 15 ns Typical into 6000 pF
Propagation Delay from Inputs to Outputs < 20 ns
Adaptive Nonoverlap Time Optimized for Large Power MOSFETs
Floating Top Driver Accommodates Applications Up to 25 V
Undervoltage Lockout to Prevent Switching when the Input
Voltage is Low
Thermal Shutdown Protection Against Overtemperature
< 1.0 mA Quiescent Current
−
Enabled
25
mA
Quiescent Current
−
Disabled
Internal TG to DRN Pulldown Resistor Prevents HV Supply−Induced
Turn On of High−Side MOSFET
Pb−Free Package is Available
PIN CONNECTIONS
DRN
TG
BST
CO
1
DRN
TG
N/C
BST
CO
DFN10
1
SO−8
8
PGND
BG
V
S
EN
10
GND
BG
N/C
V
S
EN
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
February, 2010
−
Rev. 13
1
Publication Order Number:
NCP5351/D
NCP5351
BST
V
S
+
−
+
−
4.25 V
Delay
Nonoverlap
Control
Delay
Thermal
Shutdown
V
S
BG
Level
Shifter
TG
DRN
EN
CO
PGND
Figure 1. Block Diagram
Table 1. Input−Output Truth Table
EN
L
H
H
H
H
CO
X
L
H
L
H
DRN
X
< 3.0 V
< 3.0 V
> 5.0 V
> 5.0 V
TG
L
L
H
L
H
BG
L
H
L
L
L
V
CO
tpdl
BG
V
TG
−V
DRN
tpdl
TG
tf
TG
tr
TG
tpdh
TG
(Nonoverlap)
tf
BG
tr
BG
tpdh
BG
(Nonoverlap)
V
BG
V
DRN
4.0 V
Figure 2. Timing Diagram
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2
+
−
4.0 V
NCP5351
PACKAGE PIN DESCRIPTION
Pin Number
SO−8
1
2
3
DFN−10
1
2
4
Pin Symbol
DRN
TG
BST
Description
The switching node common to the high and low−side FETs. The high−side (TG)
driver and supply (BST) are referenced to this pin.
Driver output to the high−side MOSFET gate.
Bootstrap supply voltage input. In conjunction with a Schottky diode to V
S
, a 0.1
mF
to
1.0
mF
ceramic capacitor connected between BST and DRN develops supply voltage
for the high−side driver (TG).
Logic level control input produces complementary output states
−
no inversion at TG;
inversion at BG.
Not Connected.
Logic level enable input forces TG and BG low, and supply current to 10
mA
when
EN is low.
Power supply input. A 0.1
mF
to 1.0
mF
ceramic capacitor should be connected from
this pin to PGND.
Driver output to the low−side (synchronous rectifier) MOSFET gate.
Ground.
Ground.
4
−
5
6
7
8
−
5
3, 8
6
7
9
−
10
CO
N/C
EN
V
S
BG
PGND
GND
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3
NCP5351
MAXIMUM RATINGS
−
SO−8
Rating
Operating Junction Temperature, T
J
Package Thermal Resistance: SO−8
Junction−to−Case, R
qJC
Junction−to−Ambient, R
qJA
Storage Temperature Range, T
S
Lead Temperature Soldering:
MSL Rating
Reflow: (SMD styles only) (Note 1)
Pb−Free
Value
Internally Limited
45
165
−65
to 150
230 peak
260 peak
1
Unit
°C
°C/W
°C/W
°C
°C
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. 60 seconds maximum above 183°C.
MAXIMUM RATINGS
−
DFN−10
Rating
Thermal Resistance, Junction−to−Air
Operating Ambient Temperature Range
ESD Withstand Voltage
Moisture Sensitivity
Storage Temperature Range
Junction Operating Temperature
Human Body Model (Note 2)
Machine Model (Note 2)
Symbol
R
JA
T
A
V
ESD
MSL
T
stg
T
J
Value
68.5
−30
to 85
> 2500
> 150
Level 1
−55
to 150
−30
to 125
°C
°C
Unit
°C/W
°C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. This device series contains ESD protection and exceeds the following tests:
Human Body Model, 100 pF discharge through a 1.5 kW following specification JESD22/A114.
Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
Latchup as per JESD78 Class II: > 100 mA.
MAXIMUM RATINGS
Pin Symbol
V
S
BST
DRN
Pin Name
Main Supply Voltage Input
Bootstrap Supply Voltage
Input
Switching Node
(Bootstrap Supply Return)
High−Side Driver Output
(Top Gate)
Low−Side Driver Output
(Bottom Gate)
TG & BG Control Input
Enable Input
Ground
V
MAX
6.3 V
25 V wrt/PGND
6.3 V wrt/DRN
25 V
V
MIN
−0.3
V
−0.3
V wrt/DRN
−1.0
V DC
−5.0
V for 100 ns
−6.0
V for 20 ns
−0.3
V wrt/DRN
−0.3
V
−0.3
V
−0.3
V
0V
I
SOURCE
NA
NA
4.0 A Peak (< 100
ms)
250 mA DC
4.0 A Peak (< 100
ms)
250 mA DC
4.0 A Peak (< 100
ms)
250 mA DC
1.0 mA
1.0 mA
4.0 A Peak (< 100
ms)
250 mA DC
I
SINK
4.0 A Peak (< 100
ms)
250 mA DC
4.0 A Peak (< 100
ms)
250 mA DC
NA
TG
BG
CO
EN
PGND
NOTE:
25 V wrt/PGND
6.3 V wrt/DRN
6.3 V
6.3 V
6.3 V
0V
4.0 A Peak (< 100
ms)
250 mA DC
4.0 A Peak (< 100
ms)
250 mA DC
1.0 mA
1.0 mA
NA
All voltages are with respect to PGND except where noted.
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