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NCP5355
12 V Synchronous Buck
Power MOSFET Driver
The NCP5355 is a dual MOSFET gate driver optimized to drive the
gates of both high− and low−side Power MOSFETs in a Synchronous
Buck converter. The NCP5355 is an excellent companion to
multiphase controllers that do not have integrated gate drivers, such as
ON Semiconductor’s NCP5314 or NCP5316. This architecture
provides the power supply designer greater flexibility by being able to
locate the gate drivers close to the MOSFETs.
Driving MOSFETs with a 12 V source as opposed to a 5.0 V can
significantly reduce conduction losses. Optimized internal, adaptive
nonoverlap circuitry further reduces switching losses by preventing
simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate MOSFET drain
voltages as high as 26 V. Both gate outputs can be driven low by
applying a low logic level to the Enable (EN) pin. An Undervoltage
Lockout function ensures that both driver outputs are low when the
supply voltage is low, and a Thermal Shutdown function provides the
IC with overtemperature protection.
The NCP5355 has the same pinout as the NCP5351 5.0 V
Gate Driver.
Features
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MARKING
DIAGRAMS
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
8
1
SOIC−8 EP
D SUFFIX
CASE 751AC
1
5355
ALYW
5355
ALYW
•
•
•
•
•
•
•
•
•
•
•
•
8.0 V − 14 V Gate Drive Capability
2.0 A Peak Drive Current
Rise and Fall Times < 15 ns Typical into 3300 pF
Propagation Delay from Inputs to Outputs < 30 ns
Adaptive Nonoverlap Time Optimized for Large Power MOSFETs
Floating Top Driver Accommodates Applications Up to 26 V
Undervoltage Lockout to Prevent Switching when the Input
Voltage is Low
Thermal Shutdown Protection Against Overtemperature
TG to DRN Pulldown Resistor Prevents HV Supply−Induced
Turn−On of Top MOSFET
BG to PGND Pulldown Resistor Prevents Transient Turn On of
Bottom MOSFET
Internal Bootstrap Diode Reduces Parts Count and Total
Solution Cost
Pb−Free Package is Available
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
DRN
TG
BST
CO
1
8
PGND
BG
V
S
EN
ORDERING INFORMATION
Device
NCP5355D
NCP5355DR2
NCP5355DR2G
NCP5355PDR2
Package
SOIC−8
SOIC−8
SOIC−8
(Pb−Free)
SOIC−8 EP
Shipping
†
98 Units/Rail
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2004
1
December, 2004 − Rev. 7
Publication Order Number:
NCP5355/D
NCP5355
5V
V
S
5 V Regulator
5V
Overtemp.
Shutdown
5V
5V
V
S
5V
−
+
Level Shift
Driver
UVLO
8.0/7.0 V
5V
Nonoverlap
30 ns
5V
CO
5V
2.0
mA
EN
Nonoverlap
30 ns
5V
5V
5V
Level Shift
Driver
BG
V
S
V
S
20 k
30 k
30 k
20 k
100 k
DRN
TG
5V
BST
PGND
5V
Figure 1. Block Diagram
PACKAGE PIN DESCRIPTION
Pin
1
Pin Symbol
DRN
Description
The switching node common to the high and low−side FETs. The high−side (TG) driver and supply (BST)
are referenced to this pin.
Driver output to the high−side MOSFET gate.
Bootstrap supply voltage input. In conjunction with an internal diode to V
S
, a 0.1
mF
to 1.0
mF
ceramic
capacitor connected between BST and DRN develops supply voltage for the high−side driver (TG).
Logic level control input produces complementary output states − no inversion at TG; inversion at BG.
Logic level enable input forces TG and BG low when EN is low. When EN is high (5.0 V), normal operation
ensues. No connect defaults EN high. Note: maximum high input is 5.0 V.
Power supply input. A 0.1
mF
to 1.0
mF
ceramic capacitor should be connected from this pin to PGND.
Driver output to the low−side (synchronous rectifier) MOSFET gate.
Ground.
2
3
TG
BST
4
5
CO
EN
6
7
8
V
S
BG
PGND
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2
NCP5355
MAXIMUM RATINGS
Rating
Operating Junction Temperature, T
J
Package Thermal Resistance: SOIC−8
Junction−to−Case, R
qJC
Junction−to−Ambient, R
qJA
Package Thermal Resistance: SOIC−8 EP
Junction−to−Ambient, R
qJA
(Note 1)
Storage Temperature Range, T
S
Lead Temperature Soldering: Reflow: (SMD styles only) (Note 2)
JEDEC Moisture Sensitivity
Value
Internally Limited
45
165
50
−65 to 150
230 peak
1
Unit
°C
°C/W
°C/W
°C/W
°C
°C
−
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. Ratings applies when soldered to an appropriate thermal area on the PCB.
2. 60 seconds maximum above 183°C.
MAXIMUM RATINGS
Pin Symbol
V
S
BST
DRN
Pin Name
Main Supply Voltage Input
Bootstrap Supply Voltage
Input
Switching Node
(Bootstrap Supply Return)
High−Side Driver Output
(Top Gate)
Low−Side Driver Output
(Bottom Gate)
TG and BG Control Input
Enable Input
Ground
V
MAX
15 V
30 V wrt/PGND
15 V wrt/DRN
26 V
V
MIN
−0.3 V
−0.3 V wrt/DRN
−1.0 V DC
−5.0 V for 100 ns
−6.0 V for 20 ns
−0.3 V wrt/DRN
−0.3 V
−0.3 V
−0.3 V
0V
I
SOURCE
NA
NA
2.0 A Peak (< 100
ms)
250 mA DC
2.0 A Peak (< 100
ms)
250 mA DC
2.0 A Peak (< 100
ms)
250 mA DC
1.0 mA
1.0 mA
2.0 A Peak (< 100
ms)
250 mA DC
I
SINK
2.0 A Peak (< 100
ms)
250 mA DC
2.0 A Peak (< 100
ms)
250 mA DC
NA
TG
BG
CO
EN
PGND
NOTE:
30 V wrt/PGND
15 V wrt/DRN
15 V
5.5 V
5.5 V
0V
2.0 A Peak (< 100
ms)
250 mA DC
2.0 A Peak (< 100
ms)
250 mA DC
1.0 mA
1.0 mA
NA
All voltages are with respect to PGND except where noted.
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3
NCP5355
ELECTRICAL CHARACTERISTICS
(Note 3) (0°C < T
J
< 125°C; 9.2 V < V
S
<13.2 V; 9.2 V < V
BST
< 26 V; V
EN
= Float;
C
LOAD
= 3.3 nF; unless otherwise noted.)
Parameter
DC OPERATING SPECIFICATIONS POWER SUPPLY
V
S
Quiescent Current, Operating
V
BST
Quiescent Current, Operating
UNDERVOLTAGE LOCKOUT
Start Threshold
Stop Threshold
Hysteresis
CO INPUT CHARACTERISTICS
High Threshold
Low Threshold
Input Bias Current
EN INPUT CHARACTERISTICS
High Threshold
Low Threshold
Input Bias Current
THERMAL SHUTDOWN
Overtemperature Trip Point
Hysteresis
HIGH−SIDE DRIVER
Peak Output Current
Output Resistance (Sourcing)
Output Resistance (Sinking)
LOW−SIDE DRIVER
Peak Output Current
Output Resistance (Sourcing)
Output Resistance (Sinking)
CHARGE PUMP DIODE
Forward Voltage Drop
I
D
= 100 mA
−
1.1
1.4
V
Note 4
Duty Cycle < 2.0%, Pulse Width < 100
ms,
T
J
= 125°C, V
S
= 12 V, V
BG
= 10 V
Duty Cycle < 2.0%, Pulse Width < 100
ms,
T
J
= 125°C, V
S
= 12 V, V
BG
= 2.0 V
−
−
−
2.0
1.1
1.0
−
−
−
A
W
W
Note 4
Duty Cycle < 2.0%, Pulse Width < 100
ms,
T
J
= 125°C, V
BST
− V
DRN
= 12 V, V
TG
= 10 V + V
DRN
Duty Cycle < 2.0%, Pulse Width < 100
ms,
T
J
= 125°C, V
BST
− V
DRN
= 12 V, V
TG
= 2.0 V + V
DRN
−
−
−
2.0
1.0
1.0
−
−
−
A
W
W
Note 4
Note 4
150
−
170
20
−
−
°C
°C
Both outputs respond to CO
Both outputs are low independent of CO
0 < V
EN
< 5.0 V
2.0
−
−7.0
−
−
−3.0
−
0.8
+2.0
V
V
mA
−
−
0 < V
CO
< 5.0 V
2.0
−
−
−
−
0
−
0.8
1.0
V
V
mA
V
CO
= 0 V
V
CO
= 0 V
V
CO
= 0 V
7.0
6.0
0.70
8.0
7.0
1.00
9.2
8.0
1.60
V
V
V
V
CO
= 0 V or 4.5 V; No output switching
V
CO
= 0 V or 4.5 V; No output switching
−
−
1.0
3.8
2.0
5.0
mA
mA
Test Conditions
Min
Typ
Max
Unit
3. All limits at temperature extremes are guaranteed by characterization using Standard Statistical Quality Control methods.
4. Guaranteed by design, not 100% tested in production.
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